Patents by Inventor Uwe Hoeckele

Uwe Hoeckele has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10411060
    Abstract: Embodiments related to a method of manufacturing of an imager and an imager device are shown and depicted.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: September 10, 2019
    Assignee: Infineon Technologies AG
    Inventors: Dirk Meinhold, Emanuele Bruno Bodini, Felix Braun, Hermann Gruber, Uwe Hoeckele, Dirk Offenberg, Klemens Pruegl, Ines Uhlig
  • Patent number: 10332814
    Abstract: A bonded system includes a reconstituted wafer including a hygroscopic material. A moisture barrier layer is arranged over a surface of the reconstituted wafer. An adhesive layer is arranged over a surface of the moisture barrier opposite the reconstituted wafer. A carrier is arranged over a surface of the adhesive layer opposite the moisture barrier. The adhesive layer adhesively bonds the reconstituted wafer and the carrier together.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: June 25, 2019
    Assignee: Infineon Technologies AG
    Inventors: Claus Von Waechter, Christian Altschaeffl, Holger Doepke, Uwe Hoeckele, Franz Xaver Muehlbauer, Daniel Porwol, Tobias Schmidt, Christian Schweiger, Carsten Von Koblinski
  • Publication number: 20190112182
    Abstract: A method for sealing an access opening to a cavity comprises the following steps: providing a layer arrangement having a first layer structure and a cavity arranged adjacent to the first layer structure, wherein the first layer structure has an access opening to the cavity, performing a CVD layer deposition for forming a first covering layer having a layer thickness on the first layer structure having the access opening, and performing an HDP layer deposition with a first and second substep for forming a second covering layer on the first covering layer, wherein the first substep comprises depositing a liner material layer on the first covering layer, wherein the second substep comprises partly backsputtering the liner material layer and furthermore the first covering layer in the region of the access opening, and wherein the first and second substeps are carried out alternately and repeatedly a number of times.
    Type: Application
    Filed: October 16, 2018
    Publication date: April 18, 2019
    Inventors: Gerhard Metzger-Brueckl, Alfons Dehe, Uwe Hoeckele, Johann Strasser, Arnaud Walther
  • Publication number: 20170301721
    Abstract: Embodiments related to a method of manufacturing of an imager and an imager device are shown and depicted.
    Type: Application
    Filed: May 4, 2017
    Publication date: October 19, 2017
    Inventors: Dirk Meinhold, Emanuele Bruno Bodini, Felix Braun, Hermann Gruber, Uwe Hoeckele, Dirk Offenberg, Klemens Pruegl, Ines Uhlig
  • Patent number: 9728480
    Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: August 8, 2017
    Assignee: Infineon Technologies AG
    Inventors: Kurt Matoy, Hubert Maier, Christian Krenn, Elfriede Kraxner Wellenzohn, Helmut Schoenherr, Juergen Steinbrenner, Markus Kahn, Silvana Fister, Christoph Brunner, Herbert Gietler, Uwe Hoeckele
  • Patent number: 9659992
    Abstract: Embodiments related to a method of manufacturing of an imager and an imager device are shown and depicted.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: May 23, 2017
    Assignee: Infineon Technologies AG
    Inventors: Dirk Meinhold, Emanuele Bruno Bodini, Felix Braun, Hermann Gruber, Uwe Hoeckele, Dirk Offenberg, Klemens Pruegl, Ines Uhlig
  • Publication number: 20160247739
    Abstract: A bonded system includes a reconstituted wafer including a hygroscopic material. A moisture barrier layer is arranged over a surface of the reconstituted wafer. An adhesive layer is arranged over a surface of the moisture barrier opposite the reconstituted wafer. A carrier is arranged over a surface of the adhesive layer opposite the moisture barrier. The adhesive layer adhesively bonds the reconstituted wafer and the carrier together.
    Type: Application
    Filed: February 18, 2016
    Publication date: August 25, 2016
    Applicant: Infineon Technologies AG
    Inventors: Claus Von Waechter, Christian Altschaeffl, Holger Doepke, Uwe Hoeckele, Franz Xaver Muehlbauer, Daniel Porwol, Tobias Schmidt, Christian Schweiger, Carsten Von Koblinski
  • Publication number: 20160086842
    Abstract: A method for producing a semiconductor device having a sidewall insulation includes providing a semiconductor body having a first side and a second side lying opposite the first side. At least one first trench is at least partly filled with insulation material proceeding from the first side in the direction toward the second side into the semiconductor body. The at least one first trench is produced between a first semiconductor body region for a first semiconductor device and a second semiconductor body region for a second semiconductor device. An isolating trench extends from the first side of the semiconductor body in the direction toward the second side of the semiconductor body between the first and second semiconductor body regions in such a way that at least part of the insulation material of the first trench adjoins at least a sidewall of the isolating trench. The second side of the semiconductor body is partly removed as far as the isolating trench.
    Type: Application
    Filed: December 1, 2015
    Publication date: March 24, 2016
    Inventors: CARSTEN AHRENS, RUDOLF BERGER, MANFRED FRANK, UWE HOECKELE, BERNHARD KNOTT, ULRICH KRUMBEIN, WOLFGANG LEHNERT, BERTHOLD SCHUDERER, JUERGEN WAGNER, STEFAN WILLKOFER
  • Patent number: 9236290
    Abstract: A method for producing a semiconductor device having a sidewall insulation includes providing a semiconductor body having a first side and a second side lying opposite the first side. At least one first trench is at least partly filled with insulation material proceeding from the first side in the direction toward the second side into the semiconductor body. The at least one first trench is produced between a first semiconductor body region for a first semiconductor device and a second semiconductor body region for a second semiconductor device. An isolating trench extends from the first side of the semiconductor body in the direction toward the second side of the semiconductor body between the first and second semiconductor body regions in such a way that at least part of the insulation material of the first trench adjoins at least a sidewall of the isolating trench. The second side of the semiconductor body is partly removed as far as the isolating trench.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: January 12, 2016
    Assignee: Infineon Technologies AG
    Inventors: Carsten Ahrens, Rudolf Berger, Manfred Frank, Uwe Hoeckele, Bernhard Knott, Ulrich Krumbein, Wolfgang Lehnert, Berthold Schuderer, Juergen Wagner, Stefan Willkofer
  • Publication number: 20150235917
    Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.
    Type: Application
    Filed: April 29, 2015
    Publication date: August 20, 2015
    Inventors: Kurt Matoy, Hubert Maier, Christian Krenn, Elfriede Kraxner Wellenzohn, Helmut Schoenherr, Juergen Steinbrenner, Markus Kahn, Silvana Fister, Christoph Brunner, Herbert Gietler, Uwe Hoeckele
  • Publication number: 20150194398
    Abstract: A semiconductor device and method are disclosed. The semiconductor device includes a substrate having a first region and a second region and an insulating layer arranged on the substrate. A first conductive layer is arranged in or on insulating layer in the first region and a second conductive layer is arranged in or on the insulating layer in the second region. The first conductive layer comprises a first conductive material and the second conductive layer comprises a second conductive material wherein the first conductive material is different than the second conductive material. A metal layer is arranged on the first conductive layer.
    Type: Application
    Filed: March 19, 2015
    Publication date: July 9, 2015
    Inventors: Roland Hampp, Thomas Fischer, Uwe Hoeckele
  • Patent number: 9006898
    Abstract: A semiconductor device and method are disclosed. The semiconductor device includes a substrate having a first region and a second region and an insulating layer arranged on the substrate. A first conductive layer is arranged in or on insulating layer in the first region and a second conductive layer is arranged in or on the insulating layer in the second region. The first conductive layer comprises a first conductive material and the second conductive layer comprises a second conductive material wherein the first conductive material is different than the second conductive material. A metal layer is arranged on the first conductive layer.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: April 14, 2015
    Assignee: Infineon Technologies AG
    Inventors: Roland Hampp, Thomas Fischer, Uwe Hoeckele
  • Patent number: 8999187
    Abstract: A method for manufacturing a device on a substrate includes forming a layer structure on the substrate, forming an auxiliary layer on the layer structure, forming a planarization layer on the auxiliary layer and on the substrate, exposing the auxiliary layer by a chemical mechanical polishing process and removing at least partly the auxiliary layer to form a planar surface of the remaining auxiliary layer or of the layer structure and the planarization layer. The chemical mechanical polishing process has a first removal rate with respect to the planarization layer and a second removal rate with respect to the auxiliary layer and the first removal rate is greater than the second removal rate.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: April 7, 2015
    Assignee: Infineon Technologies AG
    Inventors: Sandra Obernhuber, Christof Jalics, Joerg Adler, Uwe Hoeckele, Walter Preis, Reinhard Goellner, Tanja Ippisch, Patricia Nickut
  • Publication number: 20150087145
    Abstract: A chip includes an integrated circuit and a carbonic layer. The carbonic layer includes a graphite-like carbon, wherein a lateral conducting path through the graphite-like carbon electrically connects two circuit elements of the integrated circuit.
    Type: Application
    Filed: November 26, 2014
    Publication date: March 26, 2015
    Inventor: Uwe Hoeckele
  • Patent number: 8927419
    Abstract: A method can be used for locally rendering a carbonic isolating layer conductive. In one embodiment, a laser beam is directed onto the carbonic isolating layer so as to convert amorphous carbon of the carbonic isolating layer into graphite-like carbon. In another embodiment, the carbonic layer is heated so as to form a conducting portion of the layer so that a lateral path through the conducting portion connects two circuit elements of the integrated circuit.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: January 6, 2015
    Assignee: Infineon Technologies AG
    Inventor: Uwe Hoeckele
  • Patent number: 8866274
    Abstract: In one embodiment, a method of forming a semiconductor package comprises providing a first die having contact regions on a top surface but not on an opposite bottom surface. A dielectric liner layer is deposited under the bottom surface of the first die. The first die is attached with the deposited dielectric liner layer to a die paddle of a substrate. A bond layer is disposed between the substrate and the dielectric liner layer.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hermann Gruber, Joachim Mahler, Uwe Hoeckele, Anton Prueckl, Thomas Fischer, Matthias Schmidt
  • Publication number: 20140284663
    Abstract: Embodiments related to a method of manufacturing of an imager and an imager device are shown and depicted.
    Type: Application
    Filed: February 21, 2014
    Publication date: September 25, 2014
    Applicant: Infineon Technologies AG
    Inventors: Dirk MEINHOLD, Emanuele Bruno BODINI, Felix BRAUN, Hermann GRUBER, Uwe HOECKELE, Dirk OFFENBERG, Klemens PRUEGL, Ines UHLIG
  • Patent number: 8815743
    Abstract: A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming the through substrate via by filling an opening with a first fill material and depositing a first insulating layer over the first fill material, the first insulating layer not being deposited on sidewalls of the fill material in the opening, wherein sidewalls of the first insulating layer form a gap over the opening. The method further includes forming a void by sealing the opening using a second insulating layer.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 26, 2014
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Uwe Hoeckele, Thomas Kunstmann, Uwe Seidel
  • Publication number: 20140117511
    Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.
    Type: Application
    Filed: October 30, 2012
    Publication date: May 1, 2014
    Applicant: Infineon Technologies AG
    Inventors: Kurt Matoy, Hubert Maier, Christian Krenn, Elfriede Kraxner Wellenzohn, Helmut Schoenherr, Juergen Steinbrenner, Markus Kahn, Fister Schlemitz Silvana, Christoph Brunner, Herbert Gietler, Uwe Hoeckele
  • Publication number: 20140083973
    Abstract: A method for manufacturing a device on a substrate includes forming a layer structure on the substrate, forming an auxiliary layer on the layer structure, forming a planarization layer on the auxiliary layer and on the substrate, exposing the auxiliary layer by a chemical mechanical polishing process and removing at least partly the auxiliary layer to form a planar surface of the remaining auxiliary layer or of the layer structure and the planarization layer. The chemical mechanical polishing process has a first removal rate with respect to the planarization layer and a second removal rate with respect to the auxiliary layer and the first removal rate is greater than the second removal rate.
    Type: Application
    Filed: November 27, 2013
    Publication date: March 27, 2014
    Applicant: Infineon Technologies AG
    Inventors: Sandra Obernhuber, Christof Jalics, Joerg Adler, Uwe Hoeckele, Walter Preis, Reinhard Goellner, Tanja Schest, Patricia Nickut