Patents by Inventor Uwe Kranich

Uwe Kranich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11785332
    Abstract: The described technology is directed towards a production shot design system that facilitates previsualizing scene shots, including by members of a production crew (running client devices) in different locations in a collaborative and secure shot construction environment. Modifiable scene elements' properties and camera data can be manipulated to build a scene (shot) containing modifiable and non-modifiable scene elements. In an online, shared camera mode, changes to a scene can be communicated to other client devices, e.g., virtually immediately, so that each client device displays the change for other users to see at an interactive frame rate. Scene changes can also be made locally and/or in an offline mode before communicating to other users. In various aspects, animation and a video plane camera/video plane (e.g., greenscreen) are integrated into the production shot design system.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: October 10, 2023
    Assignee: HOME BOX OFFICE, INC.
    Inventors: Stephen Beres, Uwe Kranich
  • Publication number: 20220150419
    Abstract: The described technology is directed towards a production shot design system that facilitates previsualizing scene shots, including by members of a production crew (running client devices) in different locations in a collaborative and secure shot construction environment. Modifiable scene elements' properties and camera data can be manipulated to build a scene (shot) containing modifiable and non-modifiable scene elements. In an online, shared camera mode, changes to a scene can be communicated to other client devices, e.g., virtually immediately, so that each client device displays the change for other users to see at an interactive frame rate. Scene changes can also be made locally and/or in an offline mode before communicating to other users. In various aspects, animation and a video plane camera/video plane (e.g., greenscreen) are integrated into the production shot design system.
    Type: Application
    Filed: January 24, 2022
    Publication date: May 12, 2022
    Inventors: Stephen Beres, Uwe Kranich
  • Patent number: 11252333
    Abstract: The described technology is directed towards a production shot design system that facilitates previsualizing scene shots, including by members of a production crew (running client devices) in different locations in a collaborative and secure shot construction environment. Modifiable scene elements' properties and camera data can be manipulated to build a scene (shot) containing modifiable and non-modifiable scene elements. In an online, shared camera mode, changes to a scene can be communicated to other client devices, e.g., virtually immediately, so that each client device displays the change for other users to see at an interactive frame rate. Scene changes can also be made locally and/or in an offline mode before communicating to other users. In various aspects, animation and a video plane camera/video plane (e.g., greenscreen) are integrated into the production shot design system.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: February 15, 2022
    Assignee: HOME BOX OFFICE, INC.
    Inventors: Stephen Beres, Uwe Kranich
  • Publication number: 20200204739
    Abstract: The described technology is directed towards a production shot design system that facilitates previsualizing scene shots, including by members of a production crew (running client devices) in different locations in a collaborative and secure shot construction environment. Modifiable scene elements' properties and camera data can be manipulated to build a scene (shot) containing modifiable and non-modifiable scene elements. In an online, shared camera mode, changes to a scene can be communicated to other client devices, e.g., virtually immediately, so that each client device displays the change for other users to see at an interactive frame rate. Scene changes can also be made locally and/or in an offline mode before communicating to other users. In various aspects, animation and a video plane camera/video plane (e.g., greenscreen) are integrated into the production shot design system.
    Type: Application
    Filed: December 6, 2019
    Publication date: June 25, 2020
    Inventors: Stephen Beres, Uwe Kranich
  • Patent number: 7890740
    Abstract: A processor comprises a first mode of operation and a second mode of operation. A state of the processor in the first mode of operation comprises a first plurality of variables. The first plurality of variables comprises a return address. A state of the processor in the second mode of operation comprises a second plurality of variables in addition to the first plurality of variables. The processor is configured to perform, in case of an interrupt or exception occurring during the second mode of operation, the steps of saving the second plurality of variables and the return address to a buffer memory, replacing the return address with an address of a trampoline instruction, and switching into the first mode of operation. These steps are performed independently of an operating system.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: February 15, 2011
    Assignee: Globalfoundries Inc.
    Inventor: Uwe Kranich
  • Patent number: 7689809
    Abstract: A system comprises a master processor and at least one slave processor. A state of the master processor comprises a first plurality of variables and a state of the slave processor comprises a second plurality of variables. The system comprises a parallel mode of operation wherein data are processed by the master processor and the slave processor and a serial mode of operation wherein data are processed by the master processor. In case of an interrupt or exception occurring in the parallel mode of operation, the system performs the steps of saving at least a portion of the first plurality of variables and the second plurality of variables to a buffer memory and switching the system to the serial mode of operation. If the interrupt or exception is occurring in the slave processor, at least one of the first plurality of variables is set to a value of at least one of the second plurality of variables.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: March 30, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Uwe Kranich
  • Publication number: 20080301408
    Abstract: A system comprises a master processor and at least one slave processor. A state of the master processor comprises a first plurality of variables and a state of the slave processor comprises a second plurality of variables. The system comprises a parallel mode of operation wherein data are processed by the master processor and the slave processor and a serial mode of operation wherein data are processed by the master processor. In case of an interrupt or exception occurring in the parallel mode of operation, the system performs the steps of saving at least a portion of the first plurality of variables and the second plurality of variables to a buffer memory and switching the system to the serial mode of operation. If the interrupt or exception is occurring in the slave processor, at least one of the first plurality of variables is set to a value of at least one of the second plurality of variables.
    Type: Application
    Filed: January 16, 2008
    Publication date: December 4, 2008
    Inventor: Uwe Kranich
  • Publication number: 20080244137
    Abstract: A processor comprises a first mode of operation and a second mode of operation. A state of the processor in the first mode of operation comprises a first plurality of variables. The first plurality of variables comprises a return address. A state of the processor in the second mode of operation comprises a second plurality of variables in addition to the first plurality of variables. The processor is configured to perform, in case of an interrupt or exception occurring during the second mode of operation, the steps of saving the second plurality of variables and the return address to a buffer memory, replacing the return address with an address of a trampoline instruction, and switching into the first mode of operation. These steps are performed independently of an operating system.
    Type: Application
    Filed: October 18, 2007
    Publication date: October 2, 2008
    Inventor: Uwe Kranich
  • Publication number: 20060095593
    Abstract: A multi-processor computing device is provided that has at least two processing subsystems which each comprise a processor unit and at least one further component. In each processing subsystem, the processor unit is connected to the further component via a first link, and can be connected to at least one processor unit of another processing subsystem via a second link. The first and second links are physically decoupled, and the processing subsystems can simultaneously send data over the first and second links. There are further provided corresponding processing subsystems and multi-processor computing methods.
    Type: Application
    Filed: February 18, 2005
    Publication date: May 4, 2006
    Inventor: Uwe Kranich
  • Patent number: 7012604
    Abstract: A system and method for generating images of three-dimensional objects. The system includes one or more tracing processors, and one or more shading processors. Each of the tracing processors may be configured to (a) perform a first set of computations on a corresponding group of primary rays emanating from a viewpoint resulting in a ray tree and a set of one or more light trees for each primary ray of the corresponding group, (b) transfer the ray trees and associated light trees to one of the shading processors, and (c) repeat (a) and (b). Each of the shading processors may be configured to (d) receive ray trees and associated light trees from one of the tracing processors, (e) perform a second set of computations on the received ray trees and associated light trees to determine pixel color values, and (f) repeat (d) and (e) a plurality of times.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: March 14, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David S. Christie, Uwe Kranich
  • Patent number: 6651163
    Abstract: A mechanism for exception and interrupt handling in multithreaded multiprocessors is provided. The mechanism allows the handling of exceptions and interruptions in a multithreaded multiprocessor computer, while hiding the multiprocessor nature of the computer from the operating system. Generally, when an operating system is cognizant of the multiprocessor nature of a computer, additional overhead may be required when handling exceptions and interruptions. Due to the overhead involved in saving and restoring processing states, the performance of a processor may be significantly impacted. Additional circuitry is provided which allows the multiprocessor nature of the computer to be hidden from the operating system, while minimizing the overhead necessary for proper handling.
    Type: Grant
    Filed: March 8, 2000
    Date of Patent: November 18, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Uwe Kranich, David S. Christie
  • Patent number: 6574725
    Abstract: A processor architecture containing multiple closely coupled processors in a form of symmetric multiprocessing system is provided. The special coupling mechanism allows it to speculatively execute multiple threads in parallel very efficiently. Generally, the operating system is responsible for scheduling various threads of execution among the available processors in a multiprocessor system. One problem with parallel multithreading is that the overhead involved in scheduling the threads for execution by the operating system is such that shorter segments of code cannot efficiently take advantage of parallel multithreading. Consequently, potential performance gains from parallel multithreading are not attainable. Additional circuitry is included in a form of symmetrical multiprocessing system which enables the scheduling and speculative execution of multiple threads on multiple processors without the involvement and inherent overhead of the operating system.
    Type: Grant
    Filed: November 1, 1999
    Date of Patent: June 3, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Uwe Kranich, David S. Christie
  • Patent number: 6456891
    Abstract: A system and method for transparent handling of extended register states. A set of additional registers, or an extended register file, is added to the base architecture of a microprocessor. The extended register file includes two dedicated registers and a plurality of general-use registers. The extended register file is mapped to a region in main memory. One dedicated register of the extended register file stores the physical base address of the memory region. Another dedicated register of the extended register file is used to store bits to indicate the status of the extended register file. A set of extended instructions is implemented for transferring data to and from the extended register file.
    Type: Grant
    Filed: October 27, 1999
    Date of Patent: September 24, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Uwe Kranich, David S. Christie
  • Patent number: 6230259
    Abstract: A microprocessor having a standard register set and an extended register set, which is configured to save its state upon suspension of either an extended register process or a standard register processor. The microprocessor is configured to execute both standard register instruction sequences and extended register instruction sequences. A first memory is provided for storing a state of the microprocessor when a standard register instruction set sequence is suspended. The microprocessor further comprises a second memory for storing a microprocessor state upon suspension of the microprocessor executing an extended register instruction set sequence. An extended state save circuit coupled between a microprocessor core and the second memory allows the extended state of the microprocessor to be stored without modification of the operating system. As a result, the extended state of the microprocessor can be saved transparently to the operating system.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: May 8, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David S. Christie, Uwe Kranich
  • Patent number: 6185675
    Abstract: A cache memory configured to access stored instructions according to basic blocks is disclosed. Basic blocks are natural divisions in instruction streams resulting from branch instructions. The start of a basic block is a target of a branch, and the end is another branch instruction. A microprocessor configured to use a basic block oriented cache may comprise a basic block cache and a basic block sequence buffer. The basic block cache may have a plurality of storage locations configured to store basic blocks. The basic block sequence buffer also has a plurality of storage locations, each configured to store a block sequence entry. The block sequence entry may comprise an address tag and one or more basic block pointers. The address tag corresponds to the fetch address of a particular basic block, and the pointers point to basic blocks that follow the particular basic block in a predicted order.
    Type: Grant
    Filed: August 21, 1998
    Date of Patent: February 6, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Uwe Kranich, David S. Christie
  • Patent number: 6157996
    Abstract: A processor for executing computer instructions including, in one embodiment, a machine specific register (MSR) which includes a predicated execution field and an instruction decoder. The decoder is coupled to the MSR and configured to detect predicated execution information contained in the computer instruction and to include conditional execution information in the decoded instruction upon detecting an appropriate setting in the predicated execution field of the MSR. The processor further includes a first execution unit. The first execution unit is configured to detect and evaluate the conditional execution information in the decoded instruction and, if present, to execute the decoded instruction only if a condition represented by the conditional execution information is true. In another embodiment, the processor includes a standard register set and an extended register set, which includes the standard register set.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: December 5, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David S. Christie, Uwe Kranich
  • Patent number: 5900022
    Abstract: An apparatus and method for reducing the cache miss penalty in a virtual memory system is provided. The virtual memory system includes a processor core which generates virtual addresses and a cache configured to supply information in response to receipt of physical addresses. The apparatus includes a logical-to-physical translation unit which converts the virtual addresses generated by the processor core to physical addresses. The logical-to-physical translation unit includes an accurate translation unit, a speculative translation unit, and a comparing unit. The accurate translation unit accurately converts logical addresses to physical addresses. The speculative translation unit generates and transmits a speculative physical address to the cache before the accurate translation unit completes generation of the accurate physical address.
    Type: Grant
    Filed: September 3, 1997
    Date of Patent: May 4, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Uwe Kranich
  • Patent number: 5850534
    Abstract: A memory system for reducing cache snooping overhead for a multilevel cache system has a highest cache level connected to a main memory and a lowest cache level connected to a processor or other memory accessing device. Each intermediate level cache is connected to a cache level one level above and below that cache. The highest cache level detects a memory access on a shared memory bus, and determines if that memory access resides in that cache. If there is a hit in that cache, the highest cache level checks a hit flag for every storage location within that highest level cache to determine if the memory access also hits a storage location within the next lower cache level. If there is a hit in the next lower cache level, that cache also checks a hit flag for every storage location within that cache to determine if the memory access also hits a storage location within the next lower cache level.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: December 15, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Uwe Kranich
  • Patent number: 5761443
    Abstract: A multiple-transaction peripheral bus is provided with multiplexed address and data lines which is particularly adapted for portable applications. The multiple-transaction peripheral bus accommodates compatibility with existing hardware designs for a higher performance bus system with minimal conversion logic. A bus conversion bridge provides an interface between a 32-bit Peripheral Component Interconnect (PCI) bus and a 16-bit transaction Address/Data (A/D) which is associated with half the number of multiplexed address/data lines in comparison with the 32-bit PCI bus. The PCI bus accommodates data transfers between master and slave devices associated therewith, as does the narrower multiple-transaction A/D bus. The bus conversion bridge accommodates data transfers between the two buses, allowing a master device on one bus to communicate with a slave device on the other bus.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: June 2, 1998
    Assignee: Advanced Micro Systems, Inc.
    Inventor: Uwe Kranich
  • Patent number: 5761709
    Abstract: A memory system has a level 1 cache and a write cache connected to a processor, wherein the write cache has a memory address range and wherein the processor initiates a write to the write cache which is detected by the write cache. The write cache responds to the write request by storing information into the write cache if the write cache is not already full. If there is no storage location available in the write cache, a message is sent to the level 1 cache notifying that cache of this condition. The write cache responds to requests from the processor to write information stored in particular areas of the write cache into a main memory by placing that information on a external bus to be read by the main memory. The write cache then frees up those storage locations within the write cache to be used for storing subsequent writes requested by the processor.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: June 2, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Uwe Kranich