Patents by Inventor Uwe Paul Schroeder
Uwe Paul Schroeder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10311186Abstract: Methodologies and a device for assessing integrated circuit and pattern for yield risk based on 3D simulation of semiconductor patterns are provided. Embodiments include generating, with a processor, a 3D simulation of semiconductor patterns; obtaining critical dimensions of distances between layers or within a layer of the 3D simulation of semiconductor patterns; comparing the set of critical dimensions with predefined minimum dimensions; and yield scoring each of the semiconductor patterns of the 3D simulation based on the comparing step.Type: GrantFiled: April 12, 2016Date of Patent: June 4, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Jaime Bravo, Vikrant Chauhan, Piyush Pathak, Shobhit Malik, Uwe Paul Schroeder
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Patent number: 10276674Abstract: One illustrative method disclosed includes, among other things, forming a sacrificial S/D contact structure above an S/D region of a transistor device, removing at least a portion of a gate cap and at least a portion of a gate sidewall spacer to define a gate contact cavity that is positioned entirely above the active region and exposes an upper surface of a gate structure of the transistor device, and forming an internal sidewall spacer within the gate contact cavity. The method also includes performing at least one process operation to remove at least the sacrificial S/D contact structure and define a S/D contact cavity, and forming a gate contact structure within the gate contact cavity that is conductively coupled to the gate structure and forming a S/D contact structure within the S/D contact cavity that is conductively coupled to the S/D region.Type: GrantFiled: June 28, 2016Date of Patent: April 30, 2019Assignee: GLOBALFOUNDRIES Inc.Inventor: Uwe Paul Schroeder
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Patent number: 10248754Abstract: An identification of a first area of an IC design surrounding a failure component is received; and, in response, a smaller portion of the first area is selected. The smaller portion also surrounds the failure component, is smaller than the first area, and contains less circuit components than the first area. The smaller portion is matched to other areas of the IC design to identify potentially undesirable patterns of the IC design that are the same size as the first area. Additionally, the potentially undesirable patterns are grouped into pattern categories, the pattern categories are matched to known good pattern categories, and the known good patterns are removed from the potentially undesirable patterns to leave potential failure patterns. The potential failure patterns of the IC design are then output.Type: GrantFiled: May 23, 2017Date of Patent: April 2, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Uwe Paul Schroeder, Fadi Batarseh, Karthik Krishnamoorthy, Ahmed Omran
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Publication number: 20180341739Abstract: An identification of a first area of an IC design surrounding a failure component is received; and, in response, a smaller portion of the first area is selected. The smaller portion also surrounds the failure component, is smaller than the first area, and contains less circuit components than the first area. The smaller portion is matched to other areas of the IC design to identify potentially undesirable patterns of the IC design that are the same size as the first area. Additionally, the potentially undesirable patterns are grouped into pattern categories, the pattern categories are matched to known good pattern categories, and the known good patterns are removed from the potentially undesirable patterns to leave potential failure patterns. The potential failure patterns of the IC design are then output.Type: ApplicationFiled: May 23, 2017Publication date: November 29, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: Uwe Paul Schroeder, Fadi Batarseh, Karthik Krishnamoorthy, Ahmed Omran
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Patent number: 10055535Abstract: Disclosed is a method and corresponding system and program product that includes providing integrated circuit design layout(s), deconstructing the integrated circuit design layout(s) into unit-level geometric constructs, identifying anomalies in the unit-level geometric constructs, and storing anomaly data in a database.Type: GrantFiled: September 27, 2016Date of Patent: August 21, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Piyush Pathak, Robert C. Pack, Wei-Long Wang, Karthik Krishnamoorthy, Fadi S. Batarseh, Uwe Paul Schroeder, Sriram Madhavan
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Publication number: 20180089357Abstract: Disclosed is a method and corresponding system and program product that includes providing integrated circuit design layout(s), deconstructing the integrated circuit design layout(s) into unit-level geometric constructs, identifying anomalies in the unit-level geometric constructs, and storing anomaly data in a database.Type: ApplicationFiled: September 27, 2016Publication date: March 29, 2018Applicant: GLOBALFOUNDRIES Inc.Inventors: Piyush PATHAK, Robert C. PACK, Wei-Long WANG, Karthik KRISHNAMOORTHY, Fadi S. BATARSEH, Uwe Paul SCHROEDER, Sriram MADHAVAN
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Publication number: 20170373161Abstract: One illustrative method disclosed includes, among other things, forming a sacrificial S/D contact structure above an S/D region of a transistor device, removing at least a portion of a gate cap and at least a portion of a gate sidewall spacer to define a gate contact cavity that is positioned entirely above the active region and exposes an upper surface of a gate structure of the transistor device, and forming an internal sidewall spacer within the gate contact cavity. The method also includes performing at least one process operation to remove at least the sacrificial S/D contact structure and define a S/D contact cavity, and forming a gate contact structure within the gate contact cavity that is conductively coupled to the gate structure and forming a S/D contact structure within the S/D contact cavity that is conductively coupled to the S/D region.Type: ApplicationFiled: June 28, 2016Publication date: December 28, 2017Inventor: Uwe Paul Schroeder
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Publication number: 20170293704Abstract: Methodologies and a device for assessing integrated circuit and pattern for yield risk based on 3D simulation of semiconductor patterns are provided. Embodiments include generating, with a processor, a 3D simulation of semiconductor patterns; obtaining critical dimensions of distances between layers or within a layer of the 3D simulation of semiconductor patterns; comparing the set of critical dimensions with predefined minimum dimensions; and yield scoring each of the semiconductor patterns of the 3D simulation based on the comparing step.Type: ApplicationFiled: April 12, 2016Publication date: October 12, 2017Inventors: Jaime BRAVO, Vikrant CHAUHAN, Piyush PATHAK, Shobhit MALIK, Uwe Paul SCHROEDER
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Patent number: 9547741Abstract: At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received; The design comprises a first functional cell and a second functional cell. The first functional cell is placed on a circuit layout. A determination is made as to whether the first cell comprises a vertical boundary that is electrically floating. A filler cell is placed adjacent to the vertical boundary on the circuit layout in response to determining that the first cell comprises the vertical boundary that is electrically floating. The second functional cell is placed adjacent to the filler cell to form a contiguous active area on the circuit layout.Type: GrantFiled: October 20, 2014Date of Patent: January 17, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Uwe Paul Schroeder, Sushama Davar
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Publication number: 20160110489Abstract: At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received; The design comprises a first functional cell and a second functional cell. The first functional cell is placed on a circuit layout. A determination is made as to whether the first cell comprises a vertical boundary that is electrically floating. A filler cell is placed adjacent to the vertical boundary on the circuit layout in response to determining that the first cell comprises the vertical boundary that is electrically floating. The second functional cell is placed adjacent to the filler cell to form a contiguous active area on the circuit layout.Type: ApplicationFiled: October 20, 2014Publication date: April 21, 2016Inventors: Uwe Paul Schroeder, Sushama Davar
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Publication number: 20160099239Abstract: At least one method, apparatus and system disclosed herein involves performing power reduction process on a FinFET device. A first design is provided. The first design comprises a process mask definition, a FinFET device that comprises a plurality of fins characterized by said process mask, and a timing requirement relating to an operation of said FinFET device. A timing parameter of said operation of said FinFET device is determined. Based upon said timing parameter, a determination is made as to whether a drive capability of said FinFET device is above a level required to maintain said timing requirement. The process mask is modified for reducing at least one of said fins in response to said determining that said drive capability is above said level required to maintain said timing requirement.Type: ApplicationFiled: December 10, 2015Publication date: April 7, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: Uwe Paul Schroeder, Sushama Davar
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Patent number: 9245087Abstract: At least one method, apparatus and system disclosed herein involves performing power reduction process on a FinFET device. A first design is provided. The first design comprises a process mask definition, a FinFET device that comprises a plurality of fins characterized by said process mask, and a timing requirement relating to an operation of said FinFET device. A timing parameter of said operation of said FinFET device is determined. Based upon said timing parameter, a determination is made as to whether a drive capability of said FinFET device is above a level required to maintain said timing requirement. The process mask is modified for reducing at least one of said fins in response to said determining that said drive capability is above said level required to maintain said timing requirement.Type: GrantFiled: August 29, 2014Date of Patent: January 26, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Uwe Paul Schroeder, Sushama Davar
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Patent number: 9195142Abstract: Lithography masks, lithography systems, methods of manufacturing lithography masks, methods of altering material layers of semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a lithography mask includes a first pattern for at least one material layer of at least one die, the first pattern being oriented in a first position. The lithography mask includes a second pattern for at least one material layer of the at least one die, the second pattern being oriented in a second position. The second position is different than the first position.Type: GrantFiled: December 11, 2013Date of Patent: November 24, 2015Assignee: Infineon Technologies AGInventor: Uwe Paul Schroeder
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Patent number: 8853791Abstract: A memory cell includes diffusion regions formed in a substrate. Each of the diffusion regions extends along a vertical direction in a layout view at a substrate level. A first gate electrode structure at a gate electrode level is generally dogleg shaped. The first gate electrode structure extends in an oblique direction, turns to a horizontal direction, extends over and crosses the diffusion regions in the horizontal direction. A first contact structure at a contact level is generally rectangular shaped in the layout view of the cell. The first contact structure electrically connects a first source/drain region of the first diffusion region to the first gate electrode structure and the first source/drain region of the second diffusion region. The first contact structure extends from the first source/drain region of the first diffusion region to the first source/drain region of the second diffusion region at the contact level.Type: GrantFiled: November 6, 2006Date of Patent: October 7, 2014Assignee: Infineon Technologies AGInventors: Uwe Paul Schroeder, Martin Ostermayr
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Publication number: 20140099799Abstract: Lithography masks, lithography systems, methods of manufacturing lithography masks, methods of altering material layers of semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a lithography mask includes a first pattern for at least one material layer of at least one die, the first pattern being oriented in a first position. The lithography mask includes a second pattern for at least one material layer of the at least one die, the second pattern being oriented in a second position. The second position is different than the first position.Type: ApplicationFiled: December 11, 2013Publication date: April 10, 2014Applicant: Infineon Technologies AGInventor: Uwe Paul Schroeder
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Patent number: 8663877Abstract: Lithography masks, lithography systems, methods of manufacturing lithography masks, methods of altering material layers of semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a lithography mask includes a first pattern for at least one material layer of at least one die, the first pattern being oriented in a first position. The lithography mask includes a second pattern for at least one material layer of the at least one die, the second pattern being oriented in a second position. The second position is different than the first position.Type: GrantFiled: February 27, 2012Date of Patent: March 4, 2014Assignee: Infineon Technologies AGInventor: Uwe Paul Schroeder
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Patent number: 8247845Abstract: Semiconductor devices, methods of manufacturing thereof, and methods of arranging circuit components of an integrated circuit are disclosed. In one embodiment, a semiconductor device includes an array of a plurality of devices arranged in a plurality of rows. At least one electrostatic discharge (ESD) protection circuit or a portion thereof is disposed in at least one of the plurality of rows of the array of the plurality of devices.Type: GrantFiled: January 28, 2008Date of Patent: August 21, 2012Assignee: Infineon Technologies AGInventors: Uwe Paul Schroeder, David Alvarez
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Publication number: 20120155608Abstract: Lithography masks, lithography systems, methods of manufacturing lithography masks, methods of altering material layers of semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a lithography mask includes a first pattern for at least one material layer of at least one die, the first pattern being oriented in a first position. The lithography mask includes a second pattern for at least one material layer of the at least one die, the second pattern being oriented in a second position. The second position is different than the first position.Type: ApplicationFiled: February 27, 2012Publication date: June 21, 2012Applicant: INFINEON TECHNOLOGIES AGInventor: Uwe Paul Schroeder
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Patent number: 8153335Abstract: Lithography masks, lithography systems, methods of manufacturing lithography masks, methods of altering material layers of semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a lithography mask includes a first pattern for at least one material layer of at least one die, the first pattern being oriented in a first position. The lithography mask includes a second pattern for at least one material layer of the at least one die, the second pattern being oriented in a second position. The second position is different than the first position.Type: GrantFiled: May 26, 2009Date of Patent: April 10, 2012Assignee: Infineon Technologies AGInventor: Uwe Paul Schroeder
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Patent number: 8003305Abstract: A method for etching a pattern on a surface is disclosed. A mask layer is disposed over a surface and a resist is disposed over the mask layer. The resist is exposed to light through the mask exposing primary pattern and sidelobe regions. The resist is developed and the mask layer is etched according to the resist pattern. A first material is deposited over the mask layer, wherein a gap is formed beneath the material and over the primary pattern region. The material is etched back so that the gap is exposed, and the primary pattern region is etched using the first material as a mask.Type: GrantFiled: March 3, 2008Date of Patent: August 23, 2011Assignees: International Business Machines Corporation, Infineon Technologies AGInventors: Steven Scheer, Uwe Paul Schroeder