Patents by Inventor Uzma Rana
Uzma Rana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230378183Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.Type: ApplicationFiled: August 8, 2023Publication date: November 23, 2023Inventors: Anthony K. STAMPER, Uzma RANA, Siva P. ADUSUMILLI, Steven M. SHANK
-
Patent number: 11823948Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.Type: GrantFiled: March 16, 2022Date of Patent: November 21, 2023Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Uzma Rana, Anthony K. Stamper, Steven M. Shank, Brett T. Cucci
-
Patent number: 11764225Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.Type: GrantFiled: June 10, 2021Date of Patent: September 19, 2023Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Anthony K. Stamper, Uzma Rana, Siva P. Adusumilli, Steven M. Shank
-
Patent number: 11749717Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.Type: GrantFiled: May 6, 2022Date of Patent: September 5, 2023Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Uzma Rana, Anthony K. Stamper, Johnatan A. Kantarovsky, Steven M. Shank, Siva P. Adusumilli
-
Publication number: 20220399372Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.Type: ApplicationFiled: June 10, 2021Publication date: December 15, 2022Inventors: Anthony K. STAMPER, Uzma RANA, Siva P. ADUSUMILLI, Steven M. SHANK
-
Publication number: 20220384659Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure having source/drain regions; at least one isolation structure within the source/drain regions in a substrate material; and semiconductor material on a surface of the at least one isolation structure in the source/drain regions.Type: ApplicationFiled: May 26, 2021Publication date: December 1, 2022Inventors: Anthony K. STAMPER, Uzma RANA, Steven M. SHANK, Mark D. LEVY
-
Publication number: 20220262900Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.Type: ApplicationFiled: May 6, 2022Publication date: August 18, 2022Inventors: Uzma RANA, Anthony K. STAMPER, Johnatan A. KANTAROVSKY, Steven M. SHANK, Siva P. ADUSUMILLI
-
Patent number: 11380759Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.Type: GrantFiled: July 27, 2020Date of Patent: July 5, 2022Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Uzma Rana, Anthony K. Stamper, Johnatan A. Kantarovsky, Steven M. Shank, Siva P. Adusumilli
-
Publication number: 20220208599Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.Type: ApplicationFiled: March 16, 2022Publication date: June 30, 2022Inventors: Uzma RANA, Anthony K. STAMPER, Steven M. SHANK, Brett T. CUCCI
-
Patent number: 11322387Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.Type: GrantFiled: October 13, 2020Date of Patent: May 3, 2022Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Uzma Rana, Anthony K. Stamper, Steven M. Shank, Brett T. Cucci
-
Publication number: 20220115262Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.Type: ApplicationFiled: October 13, 2020Publication date: April 14, 2022Inventors: Uzma RANA, Anthony K. STAMPER, Steven M. SHANK, Brett T. CUCCI
-
Publication number: 20220028971Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.Type: ApplicationFiled: July 27, 2020Publication date: January 27, 2022Inventors: Uzma RANA, Anthony K. STAMPER, Johnatan A. KANTAROVSKY, Steven M. SHANK, Siva P. ADUSUMILLI
-
Patent number: 9966735Abstract: III-V lasers integrated with silicon photonic circuits and methods for making the same include a three-layer semiconductor stack formed from III-V semiconductors on a substrate, where a middle layer has a lower bandgap than a top layer and a bottom layer; a mirror region monolithically formed at a first end of the stack, configured to reflect emitted light in the direction of the stack; and a waveguide region monolithically formed at a second end of the stack, configured to transmit emitted light.Type: GrantFiled: June 21, 2016Date of Patent: May 8, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Cheng-Wei Cheng, Frank R. Libsch, Tak H. Ning, Uzma Rana, Kuen-Ting Shiu
-
Patent number: 9882021Abstract: A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A III-V semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench.Type: GrantFiled: February 19, 2016Date of Patent: January 30, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cheng-Wei Cheng, Edward W. Kiewra, Amlan Majumdar, Uzma Rana, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
-
Patent number: 9679775Abstract: An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Furthermore, the approach includes alloying a metal layer with a dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.Type: GrantFiled: July 15, 2016Date of Patent: June 13, 2017Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Marinus J. P. Hopstaken, Young-Hee Kim, Masaharu Kobayashi, Effendi Leobandung, Deborah A. Neumayer, Dae-Gyu Park, Uzma Rana, Tsong-Lin Tai
-
Publication number: 20160329211Abstract: An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Furthermore, the approach includes alloying a metal layer with a dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.Type: ApplicationFiled: July 15, 2016Publication date: November 10, 2016Inventors: Kevin K. Chan, Marinus J.P. Hopstaken, Young-Hee Kim, Masaharu Kobayashi, Effendi Leobandung, Deborah A. Neumayer, Dae-Gyu Park, Uzma Rana, Tsong-Lin Tai
-
Publication number: 20160301192Abstract: III-V lasers integrated with silicon photonic circuits and methods for making the same include a three-layer semiconductor stack formed from III-V semiconductors on a substrate, where a middle layer has a lower bandgap than a top layer and a bottom layer; a mirror region monolithically formed at a first end of the stack, configured to reflect emitted light in the direction of the stack; and a waveguide region monolithically formed at a second end of the stack, configured to transmit emitted light.Type: ApplicationFiled: June 21, 2016Publication date: October 13, 2016Inventors: Cheng-Wei Cheng, Frank R. Libsch, Tak H. Ning, Uzma Rana, Kuen-Ting Shiu
-
Publication number: 20160254150Abstract: An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Additionally, the approach includes performing a low temperature anneal in an oxygen free environment followed by depositing a metal layer on the dopant layer. Furthermore, the approach includes alloying the metal layer with the dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.Type: ApplicationFiled: February 27, 2015Publication date: September 1, 2016Inventors: Kevin K. Chan, Marinus J.P. Hopstaken, Young-Hee Kim, Masaharu Kobayashi, Effendi Leobandung, Deborah A. Neumayer, Dae-Gyu Park, Uzma Rana, Tsong-Lin Tai
-
Patent number: 9418846Abstract: An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Additionally, the approach includes performing a low temperature anneal in an oxygen free environment followed by depositing a metal layer on the dopant layer. Furthermore, the approach includes alloying the metal layer with the dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.Type: GrantFiled: February 27, 2015Date of Patent: August 16, 2016Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Marinus J. P. Hopstaken, Young-Hee Kim, Masaharu Kobayashi, Effendi Leobandung, Deborah A. Neumayer, Dae-Gyu Park, Uzma Rana, Tsong-Lin Tai
-
Patent number: 9407066Abstract: III-V lasers integrated with silicon photonic circuits and methods for making the same include a three-layer semiconductor stack formed from III-V semiconductors on a substrate, where a middle layer has a lower bandgap than a top layer and a bottom layer; a mirror region monolithically formed at a first end of the stack, configured to reflect emitted light in the direction of the stack; and a waveguide region monolithically formed at a second end of the stack, configured to transmit emitted light.Type: GrantFiled: July 24, 2013Date of Patent: August 2, 2016Assignee: GlobalFoundries, Inc.Inventors: Cheng-Wei Cheng, Frank R. Libsch, Tak H. Ning, Uzma Rana, Kuen-Ting Shiu