Abstract: An efficient and reliable technique is disclosed for detecting faults which occur in FIFO's, including control faults which are specific to FIFO's, as well as faults common to conventional memories, such as interport faults and faults that occur in single port memories. The technique utilizes a sequence of read, write and control operations, thereby avoiding the need to directly observe internal values within the FIFO, such as the full and empty flag values and the shift register values.

Abstract: A multiport BIST method and apparatus therefor are disclosed. The multiport BIST is advantageously based on adapting a single port BIST method by dividing the memory into sections based on the number of ports and applying the single port BIST simultaneously through all ports simultaneously (inverting where appropriate), so as to test the sections in parallel. In one embodiment of the invention, an integrated circuit device comprises a multiport memory and a built-in self-test (BIST) unit that applies a first test pattern of read and write operations to a first port of the memory and applies a second test pattern of read and write operations to a second port of the memory. The addresses in the first test pattern are offset from addresses in the second test pattern by a fixed amount. The ports preferably have adjacent bit lines, and the data values conveyed by the first and second test patterns are preferably complementary.

Abstract: A method and apparatus are disclosed for asynchronous testing of multiport memories. In one embodiment, the apparatus includes a built-in self-test (BIST) unit coupled to a multiport memory module and configured to apply a pattern of read and write test operations concurrently to multiple ports of the memory. The pattern of test operations may be any standard or customized pattern designed to establish the functionality of the multiport memory. The test operations to different ports are clocked by different clock signals so that the clock signals may be offset relative to each other by an adjustable or preset clock skew. Certain clock skews cause transitions to occur on signal lines in the memory array at the most sensitive portion(s) of a read cycle. The timing of these transitions, in combination with the presence of high-resistivity bridge faults, sufficiently disturbs the read cycle so as to cause a read error, thereby enabling detection of the bridge faults.

Abstract: An integrated circuit device is disclosed having a boundary scan chain and a hardwired BIST unit that is configurable via the control circuitry for the boundary scan chain. In one embodiment, the device includes application logic, a BIST unit, a boundary scan chain, a register, and a test access port. The application logic is the logic that provides the intended function of the chip. The BIST unit is configured to apply test patterns to the application logic to verify its functionality. The boundary scan chain is configured to sample input signals to the application logic and to control output signals from the application logic. The register stores an operational mode parameter for the BIST. The test access port provides external access to the boundary scan chain and the register, and is configured to control a clock signal to the BIST unit in accordance with the BIST operational mode parameter.

Abstract: A multiport testing procedure capable of detecting faults that occur between static random access memory ports as well as traditional cells faults uncovers all possible faults and covers all cells in the memory, without placing architectural constraints on the memory. While executing a test sequence on one port of the memory array, concurrent memory accesses are performed through other ports in the memory. If a fault exists between the port under test and any other port, then the concurrent operations interfere with the values read and/or written on the port under test, and the test uncovers the fault. Thus, for any one test port, the interport test requires only as many memory operations as the associated single port test, keeping test time to a minimum. One embodiment detects faults between the test port, which is a read/write port, and any other port, including read ports and write ports, comprising six passes through the memory.

Abstract: A CAM testing procedure detects storage logic faults, comparison logic faults, and faults caused by interactions between the storage and comparison logic for both single port and dual port CAM's. To uncover faults in the storage logic, a series of read and write operations are performed, either using a standard test sequence, such as the March C algorithm, or any other desired test sequence. The CAM test, however, intermixes comparison operations with the read and write operations to uncover faults in the comparison logic. For dual port memories, the test sequence comprises executing comparison operations concurrently with the read and/or write operations, thus revealing faults between the storage and comparison logic. For single port memories, the test sequence comprises performing a comparison operation following the read/write operations at each address, immediately verifying the comparison logic at each address.

Abstract: A method for improving the fault coverage of manufacturing tests for integrated circuits having structures such as embedded memories. In the disclosed embodiment of the invention, the integrated circuit die of a semiconductor wafer are provided with a fuse array or other circuitry capable of storing an identification number. The integrated circuit die also include an embedded memory or similar circuit and built-in self-test (BIST) and built-in self-test (BISR) circuitry. At a point early in the manufacturing test process, the fuse array of each integrated circuit die is encoded with an identification number to differentiate the die from other die of the wafer or wafer lot. The integrity of the embedded memory of each integrated circuit die is then tested at the wafer level under a variety of operating conditions via the BIST and BISR circuitry. The results of these tests are stored in ATE and associated with a particular integrated circuit die via the identification number of the die.

Abstract: An integrated circuit device is disclosed having a BIST Uinit with recolfiLgurable data retention testing for a memory array. In one embodiment, the integrated circuit device includes a memory array, a BIST unit, an externally-programmable pause count register, and a pause counter. The BIST unit is configured to apply a test pattern of memory accesses to the memory array. The test pattern preferably includes a first phase for writing data values to the memory array, a second phase for stressing the memory array, and a third phase for verifying the data values after the array has been stressed. The length of the second phase is determined by the count stored in the externally-programmable register. The count may be loaded into the pause counter by the BIST prior to the second phase. In the second phase, the BIST unit asserts a pause signal which causes the pause counter to suppress the clock signal to the BIST unit during the second phase, thereby suspending the BIST unit's activity.

Abstract: A computer-based test method and apparatus for measuring DC current drawn by an integrated circuit. The apparatus has a plurality of current measurement ranges and is first initialized to a selected one of the measurement ranges. Next, the apparatus measures the DC current drawn by the integrated circuit in the selected measurement range and increments the selected measurement range if the measured DC current is out of the selected measurement range. The apparatus repeats the steps of measuring and incrementing until the measured DC current is in the selected measurement range. The measured DC current is then compared to a specification limit for the integrated circuit.

Abstract: An efficient methodology for detecting and rejecting faulty integrated circuits with embedded memories utilizing stress factors during the manufacturing production testing process. In the disclosed embodiment of the invention, a stress factor is applied to an integrated circuit having built-in-self-test (BIST) circuitry and built-in-self-repair (BISR) circuitry. A BIST run is then performed on a predetermined portion of the integrated circuit to detect a set of faulty memory locations. The results of this first BIST run are stored. A second condition is applied to the die and a second BIST run is executed to generate a second set of faulty memory locations. The results of the second BIST run are stored and compared with the first result. If the results differ, the integrated circuit is rejected. Thus, a methodology for screening out field errors at the factory is disclosed using BIST/BISR circuitry.

Abstract: A test structure according to the present invention provides a technique for determining defects as a function of metal layers. The technique is implemented by dividing the test structure into individual test blocks that correspond to certain metal layers. In the disclosed embodiment, for example, a test structure formed by a semiconductor process utilizing three layers of interconnect metal includes three distinct test blocks having similar or identical underlying test logic. In a first test block, the underlying test logic is predominantly connected by the first metal layer. In a second test block, the underlying test logic is predominantly connected by the second metal layer. In a third test block, the underlying test logic is primarily connected by the third metal layer. During the testing stage, test patterns are applied to each test block and the results are tabulated.

Abstract: A test method for a memory device wherein failures that may only occur under specified worst-case conditions are converted to hard functional failures. These locations are subsequently detected and remapped by built-in self test (BIST) and built-in self-repair (BISR) circuitry. First, a test suite is performed on a memory array which includes redundant row and column locations. Typically, this test suite is performed under conditions which are most likely to induce failure. Row and column locations that are determined to be malfunctioning are scanned out of the memory device, along with the number of available redundant rows and columns. If there are sufficient redundant locations, the failing rows and columns are permanently disabled by blowing each of the corresponding fuse links. When power is subsequently applied to the memory device, BIST will detect rows and columns, including those permanently disabled, with hard functional failures. Accesses to these locations may then be redirected by BISR circuitry.

Abstract: A process which enables storage of more than two logic states in a memory cell. In one embodiment, a via is used to couple a diode between a word read line and a data read line. The via has a resistance which is set to one of a plurality of values at the time of manufacture. When the word read line is asserted, the voltage drop sustained across the via is indicative of the stored logic state. An analog-to-digital (A/D) converter is coupled to the data read line so as to sense the voltage drop and determine the state represented. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit.

Abstract: A memory device which tests the memory array under typical operating conditions. In one embodiment, the memory device incorporates a heating element to heat the memory array to a predetermined operating temperature, and a BIST (built-in self test) unit to test the memory array at the predetermined operating temperature. This may advantageously provide a method for detecting and repairing faulty memory locations that would not normally test faulty under initial power-up conditions. Broadly speaking, the present invention contemplates a memory device which comprises a memory array and a heating element on a substrate. The memory array is configured to receive a read/write signal on a read/write line, configured to receive an address on an address bus, configured to provide data to a data bus when the read/write signal indicates a read operation, and configured to store data from the data bus when the read/write signal indicates a write operation.

Abstract: A circuit and method which enables storage of more than two logic states in a memory cell by selectively setting threshold voltages of transistors in a memory array according to the present invention. In one embodiment, a memory circuit includes an array of storage transistors. Each storage transistor has a gate connected to an associated read line. When a read line is asserted, the current which flows through a selected storage transistor is indicative of the stored logic state. The current through each transistor is individually selected by setting the threshold voltage of each storage transistor during manufacture. Different transistors in the array are configured with differing threshold voltages to thereby represent different storage states. An analog-to-digital (A/D) converter is coupled to the selected storage transistor so as to sense the current and determine the state represented.

Abstract: A memory circuit which enables storage of three logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by the state of a tri-state flip-flop. By enabling the current to be detected as positive, negative, or zero, it becomes possible to represent more than one bit of information with the state of the flip-flop.

Abstract: A system and method for using a BIST generator and a BIST compactor to characterize the propagation delay time of a high-speed embedded cores and integrated circuits in general. In one embodiment, an external clock is provided having a positive edge and a negative edge. The BIST generator and test compactor is configured to apply a set of test inputs to the integrated circuit in response to the positive edge, and the BIST compactor is configured to latch a set of outputs from the integrated circuit in response to the negative edge, and determine if the set of outputs represent a valid test result. The validity determination is monitored, and as long as the test result is valid, it is determined that the propagation delay time is less than the time interval between the positive and negative transitions. The propagation delay time can then be measured by reducing the time interval until invalid test results appear.

Abstract: A memory circuit which enables storage of more than two logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by a charge stored on the transistor's gate. By enabling the current to be detected in discrete increments, it becomes possible to represent more than one bit of information with the charge stored in the memory cell. Usage of additional increments necessitates more precise storage and detection circuitry. In one embodiment, the storage circuitry uses feedback to obtain a greater logic state retrieval accuracy.

Abstract: A DRAM memory array including a temperature sensor for adjusting a refresh rate depending upon temperature. The DRAM memory array includes a plurality of memory cells, each configured to allow storage and retrieval of more than two discrete memory states. A refresh circuit is coupled to the memory array for periodically refreshing the discrete storage state of each memory cell. The temperature sensor is situated on the same semiconductor die upon which the memory array is fabricated, and generates a signal indicative of the temperature of the semiconductor die. A control circuit receives the signal from the temperature sensor and responsively generates a refresh rate signal which is provided to control the refresh rate of the refresh circuit. In one specific implementation, a ROM look-up table is coupled to the control circuit and includes a plurality of entries which indicate the desired refresh rates for particular temperatures.

Abstract: A system and process which enables storage of more than two logic states in a memory cell. In one embodiment, a programmable resistor is coupled in series with a transistor between a supply voltage and a data read line. When an access signal is asserted, the transistor provides a conductive path, and a voltage drop is sustained by the programmable resistor. The programmable resistor has a resistance which is set during a programming step to one of a plurality of values by passing a heating current through the programmable resistor for one of a corresponding plurality of predetermined lengths of time. When the access signal is asserted, the voltage drop sustained across the programmable resistor is indicative of the stored logic state. An analog-to-digital (A/D) converter is coupled to the data read line so as to sense the voltage drop and determine the state represented.