Patents by Inventor Vahid Vahedi

Vahid Vahedi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10403475
    Abstract: A tunable multi-zone injection system for a plasma processing system for plasma processing of substrates such as semiconductor wafers. The injector can include an on-axis outlet supplying process gas at a first flow rate to a central zone and off-axis outlets supplying the same process gas at a second flow rate to an annular zone surrounding the central zone. The arrangement permits modification of gas delivery to meet the needs of a particular processing regime by allowing independent adjustment of the gas flow to multiple zones in the chamber. In addition, compared to consumable showerhead arrangements, a removably mounted gas injector can be replaced more easily and economically.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: September 3, 2019
    Assignee: LAM RESEARCH CORPORATION
    Inventors: David J. Cooperberg, Vahid Vahedi, Douglas Ratto, Harmeet Singh, Neil Benjamin
  • Publication number: 20190250501
    Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.
    Type: Application
    Filed: December 18, 2018
    Publication date: August 15, 2019
    Inventors: Saravanapriyan Sriraman, Richard Wise, Harmeet Singh, Alex Paterson, Andrew D. Bailey, III, Vahid Vahedi, Richard A. Gottscho
  • Patent number: 10242883
    Abstract: A method for etching features in an OMOM stack with first layer of silicon oxide, a second layer of a metal containing material over the first layer, a third layer of silicon oxide over the second layer, and a fourth layer of a metal containing material over the third layer is provided. A hardmask is formed over the stack. The hardmask is patterned. The OMOM stack is etched through the hardmask.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: March 26, 2019
    Assignee: Lam Research Corporation
    Inventors: Joydeep Guha, Sirish K. Reddy, Kaushik Chattopadhyay, Thomas W. Mountsier, Aaron Eppler, Thorsten Lill, Vahid Vahedi, Harmeet Singh
  • Patent number: 10224221
    Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. Where multiple plasma grids are used, one or more of the grids may be movable, allowing for tenability of the plasma conditions in at least the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: March 5, 2019
    Assignee: Lam Research Corporation
    Inventors: Harmeet Singh, Thorsten Lill, Vahid Vahedi, Alex Paterson, Monica Titus, Gowri Kamarthy
  • Patent number: 10197908
    Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: February 5, 2019
    Assignee: Lam Research Corporation
    Inventors: Saravanapriyan Sriraman, Richard Wise, Harmeet Singh, Alex Paterson, Andrew D. Bailey, III, Vahid Vahedi, Richard A. Gottscho
  • Publication number: 20180374712
    Abstract: A method for etching features in an OMOM stack with first layer of silicon oxide, a second layer of a metal containing material over the first layer, a third layer of silicon oxide over the second layer, and a fourth layer of a metal containing material over the third layer is provided. A hardmask is formed over the stack. The hardmask is patterned. The OMOM stack is etched through the hardmask.
    Type: Application
    Filed: June 23, 2017
    Publication date: December 27, 2018
    Inventors: Joydeep GUHA, Sirish K. REDDY, Kaushik CHATTOPADHYAY, Thomas W. MOUNTSIER, Aaron EPPLER, Thorsten LILL, Vahid VAHEDI, Harmeet SINGH
  • Publication number: 20180247798
    Abstract: A system for controlling processing state of a plasma process is provided. One example system includes a plasma reactor having a plurality of tuning knobs for making settings to operational conditions of the plasma reactor. A plurality of sensors of the plasma reactor is included, where each of the plurality of sensors is configured to produce a data stream of information during operation of the plasma reactor for carrying out the plasma process. A controller of the plasma reactor is configured to execute a multivariate processing that is configured to use as input desired processing state values that define intended measurable conditions within a processing environment of the plasma reactor and identify current plasma processing values. The multivariate processing uses a machine learning engine that receives as inputs the desired processing state values and data streams from the plurality of sensors during processing of the plasma process.
    Type: Application
    Filed: April 30, 2018
    Publication date: August 30, 2018
    Inventors: Joydeep Guha, John Daugherty, Vahid Vahedi, Richard Alan Gottscho
  • Patent number: 10056225
    Abstract: A plasma etching system having a substrate support assembly with multiple independently controllable heater zones. The plasma etching system is configured to control etching temperature of predetermined locations so that pre-etch and/or post-etch non-uniformity of critical device parameters can be compensated for.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: August 21, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Keith William Gaff, Harmeet Singh, Keith Comendant, Vahid Vahedi
  • Patent number: 9972478
    Abstract: Methods and systems for controlling processing state of a plasma reactor to initiate processing of production substrates and/or to determine a ready state of a reactor after the reactor has been cleaned and needs to be seasoned for subsequent production wafer processing are provided. The method initiate processing of a substrate in the plasma reactor using settings for tuning knobs of the plasma reactor that are approximated to achieve desired processing state values. A plurality of data streams are received from the plasma reactor during the processing of the substrate. The plurality of data streams are used to identify current processing state values. The method includes generating a compensation vector that identifies differences between the current processing state values and the desired processing state values. The generation of the compensation vector uses machine learning to improve and refile the identification and amount of compensation needed, as identified in the compensation vector.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: May 15, 2018
    Assignee: Lam Research Corporation
    Inventors: Joydeep Guha, John Daugherty, Vahid Vahedi, Richard Alan Gottscho
  • Publication number: 20180082826
    Abstract: Methods and systems for controlling processing state of a plasma reactor to initiate processing of production substrates and/or to determine a ready state of a reactor after the reactor has been cleaned and needs to be seasoned for subsequent production wafer processing are provided. The method initiate processing of a substrate in the plasma reactor using settings for tuning knobs of the plasma reactor that are approximated to achieve desired processing state values. A plurality of data streams are received from the plasma reactor during the processing of the substrate. The plurality of data streams are used to identify current processing state values. The method includes generating a compensation vector that identifies differences between the current processing state values and the desired processing state values. The generation of the compensation vector uses machine learning to improve and refile the identification and amount of compensation needed, as identified in the compensation vector.
    Type: Application
    Filed: September 16, 2016
    Publication date: March 22, 2018
    Inventors: Joydeep Guha, John Daugherty, Vahid Vahedi, Richard Alan Gottscho
  • Publication number: 20170363950
    Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.
    Type: Application
    Filed: June 21, 2016
    Publication date: December 21, 2017
    Inventors: Saravanapriyan Sriraman, Richard Wise, Harmeet Singh, Alex Paterson, Andrew D. Bailey, III, Vahid Vahedi, Richard A. Gottscho
  • Patent number: 9818633
    Abstract: An EFEM useful for transferring wafers to and from wafer processing modules comprises an enclosure having a controlled environment therein bounded by a front wall, a back wall, first and second side walls, a top wall, and a bottom wall. The first side wall and the second side wall include two or more wafer load ports wherein each wafer load port is adapted to receive a FOUP. The front wall includes wafer ports configured to attach to respective load locks operable to allow a wafer to be transferred to a front wall cluster processing tool. The back wall includes a wafer port adapted to be in operational relationship with a back wall cluster processing tool. A robot in the EFEM enclosure is operable to transfer wafers through the wafer load ports, the first front wall wafer port, the second front wall wafer port, and the back wall wafer port.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: November 14, 2017
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Thorsten Lill, Vahid Vahedi, Candi Kristoffersen, Andrew D. Bailey, III, Meihua Shen, Rangesh Raghavan, Gary Bultman
  • Patent number: 9659783
    Abstract: A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: May 23, 2017
    Assignee: Lam Research Corporation
    Inventors: Joydeep Guha, Sirish K. Reddy, Kaushik Chattopadhyay, Thomas W. Mountsier, Aaron Eppler, Thorsten Lill, Vahid Vahedi, Harmeet Singh
  • Publication number: 20160203990
    Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. Where multiple plasma grids are used, one or more of the grids may be movable, allowing for tenability of the plasma conditions in at least the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber.
    Type: Application
    Filed: February 26, 2016
    Publication date: July 14, 2016
    Inventors: Harmeet Singh, Thorsten Lill, Vahid Vahedi, Alex Paterson, Monica Titus, Gowri Kamarthy
  • Publication number: 20160181130
    Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. Where multiple plasma grids are used, one or more of the grids may be movable, allowing for tenability of the plasma conditions in at least the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber.
    Type: Application
    Filed: February 26, 2016
    Publication date: June 23, 2016
    Inventors: Harmeet Singh, Thorsten Lill, Vahid Vahedi, Alex Paterson, Monica Titus, Gowri Kamarthy
  • Publication number: 20160111309
    Abstract: An EFEM useful for transferring wafers to and from wafer processing modules comprises an enclosure having a controlled environment therein bounded by a front wall, a back wall, first and second side walls, a top wall, and a bottom wall. The first side wall and the second side wall include two or more wafer load ports wherein each wafer load port is adapted to receive a FOUP. The front wall includes wafer ports configured to attach to respective load locks operable to allow a wafer to be transferred to a front wall cluster processing tool. The back wall includes a wafer port adapted to be in operational relationship with a back wall cluster processing tool. A robot in the EFEM enclosure is operable to transfer wafers through the wafer load ports, the first front wall wafer port, the second front wall wafer port, and the back wall wafer port.
    Type: Application
    Filed: October 17, 2014
    Publication date: April 21, 2016
    Inventors: Thorsten Lill, Vahid Vahedi, Candi Kristoffersen, Andrew D. Bailey, III, Meihua Shen, Rangesh Raghavan, Gary Bultman
  • Patent number: 9245761
    Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. Where multiple plasma grids are used, one or more of the grids may be movable, allowing for tenability of the plasma conditions in at least the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: January 26, 2016
    Assignee: Lam Research Corporation
    Inventors: Harmeet Singh, Thorsten Lill, Vahid Vahedi, Alex Paterson, Monica Titus, Gowri Kamarthy
  • Publication number: 20150235811
    Abstract: A tunable multi-zone injection system for a plasma processing system for plasma processing of substrates such as semiconductor wafers. The injector can include an on-axis outlet supplying process gas at a first flow rate to a central zone and off-axis outlets supplying the same process gas at a second flow rate to an annular zone surrounding the central zone. The arrangement permits modification of gas delivery to meet the needs of a particular processing regime by allowing independent adjustment of the gas flow to multiple zones in the chamber. In addition, compared to consumable showerhead arrangements, a removably mounted gas injector can be replaced more easily and economically.
    Type: Application
    Filed: May 4, 2015
    Publication date: August 20, 2015
    Applicant: LAM RESEARCH CORPORATION
    Inventors: David J. Cooperberg, Vahid Vahedi, Douglas Ratto, Harmeet Singh, Neil Benjamin
  • Publication number: 20150200106
    Abstract: A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask.
    Type: Application
    Filed: March 27, 2015
    Publication date: July 16, 2015
    Inventors: Joydeep GUHA, Sirish K. REDDY, Kaushik CHATTOPADHYAY, Thomas W. MOUNTSIER, Aaron EPPLER, Thorsten LILL, Vahid VAHEDI, Harmeet SINGH
  • Patent number: 9018103
    Abstract: A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: April 28, 2015
    Assignee: Lam Research Corporation
    Inventors: Joydeep Guha, Sirish K. Reddy, Kaushik Chattopadhyay, Thomas W. Mountsier, Aaron Eppler, Thorsten Lill, Vahid Vahedi, Harmeet Singh