Abstract: A guide wire arrangement, a strip arrangement, a method of forming a guide wire arrangement, and a method of forming a strip arrangement are provided. The guide wire arrangement includes a strip; a sensor being disposed on a first portion of the strip; a chip being disposed next to the sensor on a second portion of the strip, wherein the second portion of the strip is next to the first portion of the strip; wherein the strip is folded at a folding point between the first portion of the strip and the second portion of the strip such that the first portion of the strip and the second portion of the strip form a stack of strip portions.

Abstract: According to one embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure includes a first support structure, a plurality of chips formed on the first support structure and a reinforcing structure formed on the first support structure, the reinforcing structure including an outer surrounding element which surrounds the plurality of chips and extends from a surface of the first support structure to a height higher than each of the plurality of chips. A method of manufacturing a semiconductor structure is also provided.

Abstract: According to embodiments of the present invention, an implantable device for detecting variation in fluid flow rate is provided. The implantable device includes: a substrate having an active element arrangement; a sensor arrangement having a first portion that is mechanically secured and a second portion that is freely deflectable, the sensor arrangement in electrical communication with the active element arrangement, wherein the active element arrangement is configured to detect changes in deformation of the sensor arrangement and produce an output in response to the detected changes; and at least one inductive element mechanically coupled to the substrate and in electrical communication with the active element arrangement, wherein the inductive element is adapted to power the active element arrangement through inductive coupling to an excitation source, and wherein the inductive element is adapted to transmit the output associated with the detected changes in the sensor.

Abstract: According to embodiments of the present invention, a micro-sensory tip for use in blood vessels is provided. The micro-sensory tip includes: a force transmission element; at least three force detecting sensors coupled to the force transmission element, each of the at least three force detecting sensors responsive to force applied on the force transmission element, wherein each of the at least three force detecting sensors produces an output representing at least one force component of a three-dimensional Cartesian co-ordinate system, of the force experienced by the force transmission element, such that the outputs of the at least three force detecting sensors can cover the space of the three-dimensional Cartesian co-ordinate system; and an active element arrangement coupled to the at least three force detecting sensors, the active element arrangement configured to process the output from the at least three force detecting sensors.

Abstract: According to one embodiment of the present invention, a substrate arrangement is provided. The substrate arrangement includes a first substrate; a second substrate positioned above the first substrate, the second substrate comprising a first through hole; a third substrate positioned above the second substrate, the third substrate comprising a second through hole; a first electrically conductive interconnect pillar positioned on the first substrate and extending from the first substrate through the first through hole to electrically contact the third substrate; and a second electrically conductive interconnect pillar positioned on the second substrate and extending from the second substrate through the second through hole. A method of manufacturing a substrate arrangement is also provided.

Abstract: According to one embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure includes a first support structure, a plurality of chips formed on the first support structure and a reinforcing structure formed on the first support structure, the reinforcing structure including an outer surrounding element which surrounds the plurality of chips and extends from a surface of the first support structure to a height higher than each of the plurality of chips. A method of manufacturing a semiconductor structure is also provided.

Abstract: A die package and a method for manufacturing the die package are provided.

Abstract: An electronic package (200) comprises a substrate (201), a first carrier layer arrangement (211) adapted to dissipate heat from at least one chip (217) mounted thereon, and a heat exchanger (221) mounted on the first carrier layer arrangement. The first carrier layer arrangement comprises at least one internal microchannel (213), which is fluidically interconnected with the heat exchanger (221) though an inlet (215) and an outlet (219). The heat exchange further comprises a pump (223) controlling fluid flow through the microchannel (213). The package may further comprise a stack of carrier layer arrangements (211), each of which may have one or more chips (217) mounted thereon.

Abstract: A magnetically-assisted chip assembly unit for assembling at least one chip having a mounting surface and an attachment surface, wherein the attachment surface supports a magnetisable layer thereon and opposes said mounting surface, onto a substrate that has a corresponding chip mounting surface. The unit comprises a template wafer having at least one recess adapted to accommodate therein said chip; and a master wafer having at least one magnetisable element; wherein the template wafer is mounted on the master wafer and said magnetisable element is located at least proximate to the at least one recess such that the magnetisable element is capable of manipulating the chip into the recess, via its magnetisable layer when the magnetisable element is magnetized and generates a magnetic field. Once in the recess, the attachment surface of the chip faces at least a portion of the recess and the mounting surface of the chip faces an opening of the recess.

Abstract: A new method to form shielded vias with microstrip ground plane in the manufacture of an integrated circuit device is achieved. The method comprises, first, providing a substrate. The substrate is etched through to form holes for planned shielded vias with microstrip ground plane. A first dielectric layer is formed overlying the top side of the substrate and lining the holes. A first conductive layer is deposited overlying the first dielectric layer and lining the holes. A second dielectric layer is deposited overlying the first conductive layer and lining the holes. A second conductive layer is deposited overlying the second dielectric layer and filling the holes. The second conductive layer is planarized to confine the second conductive layer to the holes and to thereby complete the shielded vias with microstrip ground plane. Silicon carrier modules and stacked, multiple integrated circuit modules are formed using shielded vias with microstrip ground plane to improve RF performance.

Abstract: A new method to form shielded vias with microstrip ground plane in the manufacture of an integrated circuit device is achieved. The method comprises, first, providing a substrate. The substrate is etched through to form holes for planned shielded vias with microstrip ground plane. A first dielectric layer is formed overlying the top side of the substrate and lining the holes. A first conductive layer is deposited overlying the first dielectric layer and lining the holes. A second dielectric layer is deposited overlying the first conductive layer and lining the holes. A second conductive layer is deposited overlying the second dielectric layer and filling the holes. The second conductive layer is planarized to confine the second conductive layer to the holes and to thereby complete the shielded vias with microstrip ground plane. Silicon carrier modules and stacked, multiple integrated circuit modules are formed using shielded vias with microstrip ground plane to improve RF performance.

Abstract: A new method to form shielded vias with microstrip ground plane in the manufacture of an integrated circuit device is achieved. The method comprises, first, providing a substrate. The substrate is etched through to form holes for planned shielded vias with microstrip ground plane. A first dielectric layer is formed overlying the top side of the substrate and lining the holes. A first conductive layer is deposited overlying the first dielectric layer and lining the holes. A second dielectric layer is deposited overlying the first conductive layer and lining the holes. A second conductive layer is deposited overlying the second dielectric layer and filling the holes. The second conductive layer is planarized to confine the second conductive layer to the holes and to thereby complete the shielded vias with microstrip ground plane. Silicon carrier modules and stacked, multiple integrated circuit modules are formed using shielded vias with microstrip ground plane to improve RF performance.

Abstract: A wafer level package formed on an integrated circuit chip having bondpads and a fabrication method therefor is disclosed. The wafer level package comprises at least one first, second and third separation layer having at least one first and second conductive layer formed in-between the separation layers. The at least one first conductive layer is formed on the at least one first separation layer and is coupled to the bondpads. The at least one second conductive layer is formed on the at last one second separation layer wherein the at least one second conductive layer is electrically coupled to the at least one first conductive layer. The at least one third separation layer allows solder to be attached to the at least one second conductive layer for electrically coupling the solder to the bondpads. A chip ground plane is laid in the integrated circuit chip for providing a ground to the at least one first conductive layer and the solder.

Abstract: A process for packaging semiconductor devices for flip chip and wire bond applications, wherein specific materials of the semiconductor devices are protected during device processing sequences and dicing procedures, has been developed. After definition of copper interconnect structures surrounded by a low k insulator layer, a protective, first photosensitive polymer layer comprised with a low dielectric constant is applied. After definition of openings in the first photosensitive polymer layer exposing portions of the top surface of the copper interconnect structures, a dicing lane opening is defined in materials located between copper interconnect structures. Conductive redistribution shapes are formed on the copper interconnect structures exposed in the openings in the first photosensitive polymer layer, followed by application of a protective, second photosensitive polymer layer.

Abstract: In an improved method for bumped wafer thinning, a wafer is provided having a front side and a back side wherein contact pads are formed on the top surface. A dry film is formed on the front side of the wafer and openings are provided in the dry film to the contact pads. Interconnections, such as solder bumps, are formed within the openings on the contact pads. A back grind tape or carrier is attached to the dry film and overlying the interconnections. Thereafter, the wafer is thinned from the back side of the wafer.

Abstract: A semiconductor chip comprising at least one contact area for electrically connecting the chip to a substrate, the contact area comprising a metallic contact pad covered by a seed layer and at least one copper interconnect post having a base surface directly contacting the contact area and extending from the contact area in a direction at least substantially perpendicular thereto in a tapered manner. A method for manufacturing a semiconductor chip with a copper interconnect post is also disclosed.

Abstract: A process for packaging semiconductor devices for flip chip and wire bond applications, wherein specific materials of the semiconductor devices are protected during device processing sequences and dicing procedures, has been developed. After definition of copper interconnect structures surrounded by a low k insulator layer, a protective, first photosensitive polymer layer comprised with a low dielectric constant is applied. After definition of openings in the first photosensitive polymer layer exposing portions of the top surface of the copper interconnect structures, a dicing lane opening is defined in materials located between copper interconnect structures. Conductive redistribution shapes are formed on the copper interconnect structures exposed in the openings in the first photosensitive polymer layer, followed by application of a protective, second photosensitive polymer layer.

Abstract: A wafer level package formed on an integrated circuit chip having bondpads and a fabrication method therefor is disclosed. The wafer level package comprises at least one first, second and third separation layer having at least one first and second conductive layer formed in-between the separation layers. The at least one first conductive layer is formed on the at least one first separation layer and is coupled to the bondpads. The at least one second conductive layer is formed on the at last one second separation layer wherein the at least one second conductive layer is electrically coupled to the at least one first conductive layer. The at least one third separation layer allows solder to be attached to the at least one second conductive layer for electrically coupling the solder to the bondpads. A chip ground plane is laid in the integrated circuit chip for providing a ground to the at least one first conductive layer and the solder.

Abstract: In an improved method for bumped wafer thinning, a wafer is provided having a front side and a back side wherein contact pads are formed on the top surface. A dry film is formed on the front side of the wafer and openings are provided in the dry film to the contact pads. Interconnections, such as solder bumps, are formed within the openings on the contact pads. A back grind tape or carrier is attached to the dry film and overlying the interconnections. Thereafter, the wafer is thinned from the back side of the wafer.

Abstract: A new method to form shielded vias with microstrip ground plane in the manufacture of an integrated circuit device is achieved. The method comprises, first, providing a substrate. The substrate is etched through to form holes for planned shielded vias with microstrip ground plane. A first dielectric layer is formed overlying the top side of the substrate and lining the holes. A first conductive layer is deposited overlying the first dielectric layer and lining the holes. A second dielectric layer is deposited overlying the first conductive layer and lining the holes. A second conductive layer is deposited overlying the second dielectric layer and filling the holes. The second conductive layer is planarized to confine the second conductive layer to the holes and to thereby complete the shielded vias with microstrip ground plane. Silicon carrier modules and stacked, multiple integrated circuit modules are formed using shielded vias with microstrip ground plane to improve RF performance.