Abstract: An automatic machine for producing reinforcement blanks, in particular of the type of reinforcement chairs, the automatic machine comprising two outer moulding units (A, A?) and two inner moulding units (B, B?), wherein each of the moulding units (A, A? and B, B?) comprises a pair of mandrels—a movable mandrel (8, 5) and a stationary mandrel (7, 6) connected to a power mechanism (11, 2). A method for producing reinforcement chairs from reinforcement sections comprising simultaneously forming the two support legs of the reinforcement chair in mutually opposite directions by the two outer moulding units (A, A?) and then simultaneously forming the two vertical supports of the reinforcement chair by the two inner moulding units (B, B?).

Abstract: An automatic machine for producing reinforcement blanks, in particular of the type of reinforcement chairs, the automatic machine comprising two outer moulding units (A, A?) and two inner moulding units (B, B?), wherein each of the moulding units (A, A? and B, B?) comprises a pair of mandrels—a movable mandrel (8, 5) and a stationary mandrel (7, 6) connected to a power mechanism (11, 2). A method for producing reinforcement chairs from reinforcement sections comprising simultaneously forming the two support legs of the reinforcement chair in mutually opposite directions by the two outer moulding units (A, A?) and then simultaneously forming the two vertical supports of the reinforcement chair by the two inner moulding units (B, B?).

Abstract: The present invention generally provides methods and apparatuses that are adapted to form a high quality dielectric gate layer on a substrate. Embodiments contemplate a method wherein a metal plasma treatment process is used in lieu of a standard nitridization process to form a high dielectric constant layer on a substrate. Embodiments further contemplate an apparatus adapted to “implant” metal ions of relatively low energy in order to reduce ion bombardment damage to the gate dielectric layer, such as a silicon dioxide layer and to avoid incorporation of the metal atoms into the underlying silicon. In general, the process includes the steps of forming a high-k dielectric and then terminating the surface of the deposited high-k material to form a good interface between the gate electrode and the high-k dielectric material.

Abstract: The present invention generally provides methods and apparatuses that are adapted to form a high quality dielectric gate layer on a substrate. Embodiments contemplate a method wherein a metal plasma treatment process is used in lieu of a standard nitridization process to form a high dielectric constant layer on a substrate. Embodiments further contemplate an apparatus adapted to “implant” metal ions of relatively low energy in order to reduce ion bombardment damage to the gate dielectric layer, such as a silicon dioxide layer and to avoid incorporation of the metal atoms into the underlying silicon. In general, the process includes the steps of forming a high-k dielectric and then terminating the surface of the deposited high-k material to form a good interface between the gate electrode and the high-k dielectric material.

Abstract: Apparatus and method for processing a substrate are provided. The apparatus for processing a substrate comprises: a chamber having a first electrode; a substrate support disposed in the chamber and providing a second electrode; a high frequency power source electrically connected to either the first or the second electrode; a low frequency power source electrically connected to either the first or the second electrode; and a variable impedance element connected to one or more of the electrodes. The variable impedance element may be tuned to control a self bias voltage division between the first electrode and the second electrode. Embodiments of the invention substantially reduce erosion of the electrodes, maintain process uniformity, improve precision of the etch process for forming high aspect ratio sub-quarter-micron interconnect features, and provide an increased etch rate which reduces time and costs of production of integrated circuits.

Abstract: We have discovered a method which permits plasma etching at a constant etch rate. The constant etch rate is achieved by controlling plasma process parameters so that a stable plasma is obtained, with a portion of the power deposited to the plasma being a capacitive contribution, and a portion being an inductive contribution. In particular, a stable plasma may be obtained within two process regions. In the first region, the gradient of the capacitive power to the power applied to the inductively coupled source for plasma generation [∂Pcap/∂PRF] is greater than 0. In the second region, plasma stability is controlled so that [∂Pcap/∂PRF] is less than 0 and so that Pcap<<PRF. Typically, the magnitude of Pcap is less than about 10% of the magnitude of PRF. Operation of the etch process in a stable plasma region enables use of a timed etch end point.

Abstract: The present invention generally provides a method for processing a semiconductor substrate, wherein the method includes positioning a substrate in a processing chamber having at least a first and second coils positioned above the substrate and supplying a first electrical current to the first coil. The method further includes supplying a second current to the second coil and regulating a current ratio of electrical current supplied to the first and second coils with a power distribution network in communication with the first and second coils and a single power supply.

Abstract: Apparatus and method for processing a substrate are provided. The apparatus for processing a substrate comprises: a chamber having a first electrode; a substrate support disposed in the chamber and providing a second electrode; a high frequency power source electrically connected to either the first or the second electrode; a low frequency power source electrically connected to either the first or the second electrode; and a variable impedance element connected to one or more of the electrodes. The variable impedance element may be tuned to control a self bias voltage division between the first electrode and the second electrode. Embodiments of the invention substantially reduce erosion of the electrodes, maintain process uniformity, improve precision of the etch process for forming high aspect ratio sub-quarter-micron interconnect features, and provide an increased etch rate which reduces time and costs of production of integrated circuits.

Abstract: Method and apparatus for distributing power from a single power source to a plurality of coils disposed on a processing chamber which provides controllable plasma uniformity across a substrate disposed in the processing chamber. The apparatus for distributing power from a power source to two or more coils disposed on a process chamber comprises a connection between the power source and a first coil, a series capacitor connected between the power source and the second coil, and a shunt capacitor connected to a node between the second coil and the power source. The method for distributing power from one power source to a plurality of coils comprises connecting a first coil between the power source and a ground connection, connecting a first power distribution network to the power source, wherein each power distribution network comprises a series capacitor and a shunt capacitor, and connecting a second coil between the first power distribution network and a ground connection.

Abstract: In accordance with the present invention, process parameters are controlled to provide a stable etch plasma. We have discovered that it is possible to operate a stable plasma with a portion of the power deposited to the plasma being a capacitive contribution and a portion of the power deposited being an inductive contribution. In particular, a stable plasma may be obtained within two process regions. In the first region, the gradient of the capacitive power to the power applied to the inductively coupled source for plasma generation [∂Pcap/∂PRF] is greater than 0. In the second region, plasma stability is controlled so that [∂Pcap/∂PRF] is less than 0 and so that Pcap<<PRF. Typically, the magnitude of Pcap is less than about 10% of the magnitude of PRF.

Abstract: In accordance with the present invention, process parameters are controlled to provide a stable etch plasma. We have discovered that it is possible to operate a stable plasma with a portion of the power deposited to the plasma being a capacitive contribution and a portion of the power deposited being an inductive contribution. In particular, a stable plasma may be obtained within two process regions. In the first region, the gradient of the capacitive power to the power applied to the inductively coupled source for plasma generation [∂Pcap/∂PRF] is greater than 0. In the second region, plasma stability is controlled so that [∂Pcap/∂PRF] is less than 0 and so that Pcap<<PRF. Typically, the magnitude of Pcap is less than about 10% of the magnitude of PRF.

Abstract: The present invention generally provides a method for processing a semiconductor substrate, wherein the method includes positioning a substrate in a processing chamber having at least a first and second coils positioned above the substrate and supplying a first electrical current to the first coil. The method further includes supplying a second current to the second coil and regulating a current ratio of electrical current supplied to the first and second coils with a power distribution network in communication with the first and second coils and a single power supply.

Abstract: A method and apparatus for estimating voltage on a wafer located in a process chamber. A probe, embedded in a wall of the process chamber, detects voltage levels generated by a plasma within the process chamber. A relationship between the detected plasma voltage level and the wafer voltage is determined.

Abstract: Apparatus and a concomitant method for estimating voltage on a wafer located in a process chamber. A probe, attached externally to a wall of the process chamber, detects voltage levels generated by a plasma within said process chamber. A relationship between the detected plasma voltage level and the wafer voltage is determined.