Patents by Inventor Valeri G. Gorokhov

Valeri G. Gorokhov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7003650
    Abstract: A method and apparatus for solving the output dependence problem in an explicit parallelism architecture microprocessor with consideration for implementation of the precise exception. In case of an output dependence hazard, the issue into bypass of a result of the earlier issued operation having an output hazard is cancelled. Latencies of short instructions are aligned by including additional stages on the way of writing the results into the register file in shorter executive units, which allows to save the issue order while writing the results into the register file. For long and unpredictable latencies of the instructions, writing of the result of the earlier issued operation having an output dependence hazard into the register file is cancelled after checking for no precise exception condition. All additional stages are connected to the bypass not to increase the result access time in case of this result use in the following operations.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: February 21, 2006
    Assignee: Elbrus International
    Inventors: Boris A. Babaian, Valeri G. Gorokhov, Feodor A. Gruzdov, Yuli K. Sakhin, Vladimir V. Rudometov, Valdimir Y. Volkonsky
  • Publication number: 20020169944
    Abstract: A method and apparatus for solving the output dependence problem in an explicit parallelism architecture microprocessor with consideration for implementation of the precise exception. In case of an output dependence hazard, the issue into bypass of a result of the earlier issued operation having an output hazard is cancelled. Latencies of short instructions are aligned by including additional stages on the way of writing the results into the register file in shorter executive units, which allows to save the issue order while writing the results into the register file. For long and unpredictable latencies of the instructions, writing of the result of the earlier issued operation having an output dependence hazard into the register file is cancelled after checking for no precise exception condition. All additional stages are connected to the bypass not to increase the result access time in case of this result use in the following operations.
    Type: Application
    Filed: December 11, 2001
    Publication date: November 14, 2002
    Applicant: Elbrus International
    Inventors: Boris A. Babaian, Valeri G. Gorokhov, Feodor A. Gruzdov, Vladimir V. Rudometov, Yuli K. Sakhin, Vladimir Y. Volkonsky
  • Patent number: 5889985
    Abstract: An array prefetch system improves processor performance by automatically tuning a statically compiled and compacted loop program at run-time to accommodate variations in latency of memory read operations. Using the array prefetch system, the processor, while awaiting completion of a data access, continues to generate requests for subsequent iterations rather than fully halting execution until a read access is finished.
    Type: Grant
    Filed: October 18, 1996
    Date of Patent: March 30, 1999
    Assignee: Elbrus International
    Inventors: Boris A. Babaian, Valeri G. Gorokhov, Feodor A. Gruzdov, Yuli Kh. Sakhin, Vladimir Yu. Volkonski
  • Patent number: 5794029
    Abstract: For certain classes of software pipelined loops, prologue and epilogue control is provided by loop control structures, rather than by predicated execution features of a VLIW architecture. For loops compatible with two simple constraints, code elements are not required for disabling garbage operations during prologue and epilogue loop periods. As a result, resources associated with implementation of the powerful architectural feature of predicated execution need not be squandered to service loop control. In particular, neither increased instruction width nor an increased number of instructions in the loop body is necessary to provide loop control in accordance with the present invention. Fewer service functions are required in the body of a loop. As a result, loop body code can be more efficiently scheduled by a compiler and, in some cases, fewer instructions will be required, resulting in improved loop performance.
    Type: Grant
    Filed: October 18, 1996
    Date of Patent: August 11, 1998
    Assignee: Elbrus International Ltd.
    Inventors: Boris A. Babaian, Valeri G. Gorokhov, Feodor A. Gruzdov, Yuli Kh. Sakhin, Vladimir Yu. Volkonski