Abstract: A method and apparatus for a semiconductor device having a semiconductor device having increased conductive material reliability is described. That method and apparatus comprises forming a conductive path on a substrate. The conductive path made of a first material. A second material is then deposited on the conductive path. Once the second material is deposited on the conductive path, the diffusion of the second material into the conductive path is facilitated. The second material has a predetermined solubility to substantially diffuse to grain boundaries within the first material.

Abstract: Metal alloy barrier layers formed of a group VIII metal alloyed with boron (B) and/or phosphorous (P) and an at least one element from glyoxylic acid, such as carbon (C), hydrogen (H), or carbon and hydrogen (CH) formed by electoless plating are described. These barrier layers may be used as a barrier layer over copper bumps that are soldered to a tin-based solder in a die package. Such barrier layers may also be used as barrier layer liners within trenches in which copper interconnects or vias are formed and as capping layers over copper interconnects or vias to prevent the electromigration of copper.

Abstract: A method of depositing a metal cladding on conductors in a damascene process is described. The potential between, for instance, cobalt ions in electroless solution and the surface of an ILD between the conductors is adjusted so as to repel the metal from the ILD.

Abstract: A metal oxide sensor is provided on a semiconductor substrate to provide on-chip sensing of gases. The sensor may include a metal layer that may have pores formed by lithography to be of a certain width. The top metal layer may be oxidized resulting in a narrowing of the pores. Another metal layer may be formed over the oxidized layer and electrical contacts may be formed on the metal layer. The contacts may be coupled to a monitoring system that receives electrical signals indicative of gases sensed by the metal oxide sensor.

Abstract: Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The trenches may be filled with metal by surface activating using a catalytic metal, followed by electroless deposition of a seed layer followed by superconformal filling bottom up.

Abstract: A damascene process using a doped and undoped oxide ILD is described. The selectivity between the carbon doped and carbon free oxide provides an etching stop between the ILD's in addition to providing mechanical strength to the structure.

Abstract: An apparatus that includes an electroosmotic pump and an aqueous or nonaqueous electrolyte liquid and generates relatively low amount of hydrogen gas is described herein. The apparatus may further include a hydrogen absorber.

Abstract: A method, apparatus, system, and machine-readable medium for an interconnect structure in a semiconductor device and its method of formation is disclosed. Embodiments comprise a carbon-doped and silicon-doped interconnect having a concentration of silicon to avoid to forming a copper silicide layer between an interconnect and a passivation layer. Some embodiments provide unexpected results in electromigration reliability in regards to activation energy and/or mean time to failure.

Abstract: Numerous embodiments of a method to assemble nano-materials on a platform are described. In one embodiment, a nano-material is functionalized with a first bondable group. The functionalized nano-material is disposed on an assembly platform having an electrode to form a first layer. Additional layers of the nano-material may be formed above the first layer to form a semiconductor device. In one embodiment, the nano-material may be a carbon nanotube.

Abstract: A composite carbon nanotube structure including a number of carbon nanotubes disposed in a metal matrix. The composite carbon nanotube structure may be used as a thermal interface device in a packaged integrated circuit device.

Abstract: Embodiments of a composite carbon nanotube structure comprising a number of carbon nanotubes disposed in a matrix comprised of a metal or a metal oxide. The composite carbon nanotube structures may be used as a thermal interface device in a packaged integrated circuit device.

Abstract: One or more semiconducting or conducting regions of a device such as a transistor may comprise molecular materials such as nanotubes or similar materials. Regions of a conductive alignment pattern used to align the nanotubes may be proximate to one or more ends of the nanotube. Additionally, a contact region may be proximate to each end of the nanotube to provide electrical contact to the nanotube. Nanotubes or the like may be in communication with device interconnection regions on a device substrate and may further be in communication with a package connection region on a package substrate.

Abstract: A method includes forming a barrier layer on a substrate surface including at least one contact opening; forming an interconnect in the contact opening; and reducing the electrical conductivity of the barrier layer. A method including forming a barrier layer on a substrate surface including a dielectric layer and a contact opening, depositing a conductive material in the contact opening, removing the conductive material sufficient to expose the barrier layer on the substrate surface, and reducing the electrical conductivity of the barrier layer. An apparatus including a circuit substrate including at least one active layer including at least one contact point, a dielectric layer on the at least one active layer, a barrier layer on a surface of the dielectric layer, a portion of the barrier layer having been transformed from a first electrical conductivity to a second different and reduced electrical conductivity, and an interconnect coupled to the at least one contact point.

Abstract: The present invention includes a method of providing a substrate; sequentially forming a seed layer over the substrate and forming a protection layer over the seed layer; and sequentially removing the protection layer and forming a conductor over the seed layer. The present invention further includes a structure having a substrate, the substrate having a device; an insulator disposed over the substrate, the insulator having an opening, the opening disposed over the device; a barrier layer disposed over the opening; a seed layer disposed over the barrier layer; and a protection layer disposed over the seed layer.

Abstract: A multiple stage method of electrolessly depositing a metal layer is presented. This method may have the two main stages of first forming a thin metal layer on a metal surface using an electroless plating solution containing activating agents that are highly reactive reducing agents, and second, forming a bulk metal layer over the thin metal layer by using an electroless plating solution containing mildly reactive reducing agents. Through this two stage method, the use of highly reactive reducing agents that may cause the formation of contaminant particles may be minimized. By minimizing the formation of contaminant particles in the electroless plating solution, the lifetime of the solution may be extended and the current leakage between metal interconnect lines may be reduced.

Abstract: Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interconnect line formed over the via. Often the metal layer contains a cobalt or nickel alloy and provides an etch stop layer for formation of an opening corresponding to the via. The metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer. The metal layer is conductive, rather than dielectric, and provides a shunt for passage of electrical current between the via and the interconnect line. Similar metal layers may also be used within the interconnect structures as via liner layers and via plugs.

Abstract: Seed layer treatment to remove impurities in the seed layer that might lead to the formation of voids in interconnect circuit features. In one embodiment, the seed layer is heated in a reducing environment. In another embodiment, the seed layer is washed with a surfactant that is compatible with a surfactant used when forming the remainder of the circuit feature on the seed layer. Yet another embodiment combines both techniques.

Abstract: A method comprising introducing an interconnect structure in an opening through a dielectric over a contact point, and introducing a conductive shunt material through a chemically-induced oxidation-reduction reaction. A method comprising introducing an interconnect structure in an opening through a dielectric over a contact point, introducing a conductive shunt material having an oxidation number over an exposed surface of the interconnect structure, and reducing the oxidation number of the shunt. An apparatus comprising a substrate comprising a device having contact point, a dielectric layer overlying the device with an opening to the contact point, and an interconnect structure disposed in the opening comprising an interconnect material and a different conductive shunt material.

Abstract: Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interconnect line formed over the via. Often the metal layer contains a cobalt or nickel alloy and provides an etch stop layer for formation of an opening corresponding to the via. The metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer. The metal layer is conductive, rather than dielectric, and provides a shunt for passage of electrical current between the via and the interconnect line. Similar metal layers may also be used within the interconnect structures as via liner layers and via plugs.

Abstract: Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to electrically interconnect individual CNT's. The methods to fabricate three-dimensional carbon nanotube FET integrated circuits include the selective deposition of carbon nanotubes onto catalysts selectively formed on a conductive layer at the bottom of openings in a dielectric layer. The openings in the dielectric layer are formed using suitable techniques, such as, but not limited to, dielectric etching, and the formation of ring gate electrodes, including spacers, that provide openings for depositing self-aligned carbon nanotube semiconductor channels.