Abstract: Current probe-type memory architecture assumes that the minimum chunk of data that a probe tip can access is one entire track and perhaps only four out of five-thousand, for example, probes participate in the access thereby degrading performance. By subdividing the track into D finer chunks or data zones, D times more probes can cooperate to read out the data, hence increasing the data throughput by Dx. Each tip now only scans approximately one Dth of the track and hence the scan time is reduced by a factor D, while D probes are being utilized in parallel.

Abstract: The fabrication of seek-scan probe (SSP) memory devices involves processing on both-sides of a wafer. However, there are temperature restrictions on the mover circuitry side of the wafer and doping level constrains for either side of wafer. Using a low doped EPI layer on a highly doped substrate solves this issue and provides good STO growth.

Abstract: Methods and arrangements for data storage are discussed. Embodiments include applying a first voltage between a tip and an electrode, thereby forming a polarized domain in a ferroelectric material between 1 nanometer (nm) and 50 nm in thickness. The embodiments may also include applying another voltage through the tip, thereby generating a current responsive to an orientation of the polarized domain. The embodiments may also include measuring the current and determining the orientation of the polarized domain, based upon the measuring.

Abstract: Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.

Abstract: The fabrication of seek-scan probe (SSP) memory devices involves processing on both-sides of a wafer. However, there are temperature restrictions on the mover circuitry side of the wafer and doping level constrains for either side of wafer. Using a low doped EPI layer on a highly doped substrate solves this issue and provides good STO growth.

Abstract: Current probe-type memory architecture assumes that the minimum chunk of data that a probe tip can access is one entire track and perhaps only four out of five-thousand, for example, probes participate in the access thereby degrading performance. By subdividing the track into D finer chunks or data zones, D times more probes can cooperate to read out the data, hence increasing the data throughput by Dx. Each tip now only scans approximately one Dth of the track and hence the scan time is reduced by a factor D, while D probes are being utilized in parallel.

Abstract: Using controlled bias voltage for data retention enhancement in a ferroelectric media is generally described. In one example, an apparatus includes a ferroelectric film including one or more domains, the ferroelectric film having a first surface and a second surface, the first surface being opposite the second surface, an electrode coupled with the first surface, and an electrically conductive thin film coupled with the second surface wherein the electrically conductive thin film is sufficiently conductive that a controlled bias field applied between the electrically conductive thin film and the electrode is sufficient to grow, shrink, or actively maintain the size of the one or more domains disposed between the electrically conductive thin film and the electrode.

Abstract: An apparatus comprising a substrate, a heater formed on the substrate, and a phase-change layer formed on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer. A process comprising forming a heater on a substrate and forming a phase-change layer on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer.

Abstract: An apparatus comprising a substrate, a heater formed on the substrate, and a phase-change layer formed on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer. A process comprising forming a heater on a substrate and forming a phase-change layer on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer.

Abstract: Using controlled bias voltage for data retention enhancement in a ferroelectric media is generally described. In one example, an apparatus includes a ferroelectric film including one or more domains, the ferroelectric film having a first surface and a second surface, the first surface being opposite the second surface, an electrode coupled with the first surface, and an electrically conductive thin film coupled with the second surface wherein the electrically conductive thin film is sufficiently conductive that a controlled bias field applied between the electrically conductive thin film and the electrode is sufficient to grow, shrink, or actively maintain the size of the one or more domains disposed between the electrically conductive thin film and the electrode.

Abstract: A seek-and-scan probe memory device comprising a patterned capping layer over a phase-change media, where the patterned capping layer defines the bit locations on the phase-change media. The patterned capping layer may be formed from self-assembled structures. In other embodiments, nanostructures are formed on the bottom electrode below the phase-change media to focus an applied electric field from the probe, so as to increase bit density and contrast. The nanostructures may be a regular or random array of nanostructures, formed by using a self-assembling material. The nanostructures may be conductive or non-conductive. Other embodiments are described and claimed.

Abstract: Methods and arrangements for data storage are discussed. Embodiments include applying a first voltage between a tip and an electrode, thereby forming a polarized domain in a ferroelectric material between 1 nanometer (nm) and 50 nm in thickness. The embodiments may also include applying another voltage through the tip, thereby generating a current responsive to an orientation of the polarized domain. The embodiments may also include measuring the current and determining the orientation of the polarized domain, based upon the measuring.

Abstract: According to an embodiment of the present invention, a microelectromechanical system (MEMS) element tunes a resonator to a frequency.

Abstract: An apparatus comprising a substrate, a heater formed on the substrate, and a phase-change layer formed on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer. A process comprising forming a heater on a substrate and forming a phase-change layer on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer.

Abstract: A semiconductor substrate integrated with interconnections and circuit components. A silicon backplane is processed with silicon processing to provide electrical connectivity for circuit elements. In one embodiment functional circuit elements, e.g., MEMS, switches, filters, are integrated on the silicon backplane. In one embodiment the function circuit elements are monolithically processed into the silicon backplane. In one embodiment the silicon backplane includes interconnections for integrated circuits on different substrates to be bonded to the silicon backplane.

Abstract: A highly integrated radio front-end module. In one embodiment a semiconductor substrate is processed with various circuit components in the substrate, as well as interconnections for the various circuit components, embedding the circuit components into the substrate. One or more circuit components may be further connected with a separate integrated circuit, the separate integrated circuit bonded to the semiconductor substrate via contact points processed into the substrate.

Abstract: A surface analysis device is disclosed for identifying molecules by simultaneously scanning nanocodes on a surface of a substrate. The device includes a scanning array that is capable of simultaneously scanning the nanocodes on the surface of the substrate and an analyzer that is coupled with the scanning array. The analyzer is capable of receiving simultaneously scanned information from the scanning array and identifying molecules associated with the nanocodes.

Abstract: An electronic assembly is assembled by stacking two or more integrated circuit dies on top of one another. Prior to singulation, an opening is laser-drilled into an upper die, and subsequently filled with a conductive member. The conductive member is located on a lower die and interconnects integrated circuits of the upper and lower dies. Laser-drilling allows for faster throughput when compared to, for example, etching, especially if a small number of openings has to be formed. The opening is laser-drilled from an upper surface of the upper die all the way through the die, which allows for the use of alignment marks on an upper surface of the upper die.

Abstract: An electronic assembly is assembled by stacking two or more integrated circuit dies on top of one another. Prior to singulation, an opening is laser-drilled into an upper die, and subsequently filled with a conductive member. The conductive member is located on a lower die and interconnects integrated circuits of the upper and lower dies. Laser-drilling allows for faster throughput when compared to, for example, etching, especially if a small number of openings has to be formed. The opening is laser-drilled from an upper surface of the upper die all the way through the die, which allows for the use of alignment marks on an upper surface of the upper die.

Abstract: An electronic assembly is assembled by stacking two or more integrated circuit dies on top of one another. Prior to singulation, an opening is laser-drilled into an upper die, and subsequently filled with a conductive member. The conductive member is located on a lower die and interconnects integrated circuits of the upper and lower dies. Laser-drilling allows for faster throughput when compared to, for example, etching, especially if a small number of openings has to be formed. The opening is laser-drilled from an upper surface of the upper die all the way through the die, which allows for the use of alignment marks on an upper surface of the upper die.