Abstract: FETs including a gated oxide semiconductor spacer interfacing with a channel semiconductor. Transistors may incorporate a non-oxide channel semiconductor, and one or more oxide semiconductors disposed proximal to the transistor gate electrode and the source/drain semiconductor, or source/drain contact metal. In advantageous embodiments, the oxide semiconductor is to be gated by a voltage applied to the gate electrode (i.e., gate voltage) so as to switch the oxide semiconductor between insulating and semiconducting states in conjunction with gating the transistor's non-oxide channel semiconductor between on and off states.

Abstract: Techniques and mechanisms for providing a space efficient complementary metal-oxide-semiconductor (CMOS) circuit. In an embodiment, a p-type transistor of a circuit is to conduct current in a direction parallel to a surface of a semiconductor substrate, wherein an n-type thin film transistor (TFT) of the circuit is to conduct current in a direction which is orthogonal to the surface. A first interconnect is directly coupled to each of the two transistors, wherein the first interconnect, a high mobility channel structure of the n-type TFT, and a source or drain of the p-type transistor are on the same line of direction. A second interconnect comprises a conductive path which extends to respective gates of the p-type transistor and the n-type TFT, wherein the conductive path is limited to a region over a footprint of the p-type transistor. In another embodiment, functionality of a logical inverter is provided with the circuit.

Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip.

Abstract: Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed.

Abstract: Techniques and mechanisms for operating transistors that are in a stacked configuration. In an embodiment, an integrated circuit (IC) device includes transistors arranged along a line of direction which is orthogonal to a surface of a semiconductor substrate. A first epitaxial structure and a second epitaxial structure are coupled, respectively, to a first channel structure of a first transistor and a second channel structure of a second transistor. The first epitaxial structure and the second epitaxial structure are at different respective levels relative to the surface of the semiconductor substrate. A dielectric material is disposed between the first epitaxial structure and the second epitaxial structure to facilitate electrical insulation of the channels from each other. In another embodiment, the stacked transistors are coupled to provide a complementary metal-oxide-semiconductor (CMOS) inverter circuit.

Abstract: Embodiments include a threshold switching selector. The threshold switching selector may include a threshold switching layer and a semiconductor layer between two electrodes. A memory cell may include the threshold switching selector coupled to a storage cell. The storage cell may be a PCRAM storage cell, a MRAM storage cell, or a RRAM storage cell. In addition, a RRAM device may include a RRAM storage cell, coupled to a threshold switching selector, where the threshold switching selector may include a threshold switching layer and a semiconductor layer, and the semiconductor layer of the threshold switching selector may be shared with the semiconductor layer of the RRAM storage cell.

Abstract: Techniques and mechanisms for operating transistors that are in a stacked configuration. In an embodiment, an integrated circuit (IC) device includes transistors arranged along a line of direction which is orthogonal to a surface of a semiconductor substrate. A first epitaxial structure and a second epitaxial structure are coupled, respectively, to a first channel structure of a first transistor and a second channel structure of a second transistor. The first epitaxial structure and the second epitaxial structure are at different respective levels relative to the surface of the semiconductor substrate. A dielectric material is disposed between the first epitaxial structure and the second epitaxial structure to facilitate electrical insulation of the channels from each other. In another embodiment, the stacked transistors are coupled to provide a complementary metal-oxide-semiconductor (CMOS) inverter circuit.

Abstract: Techniques and mechanisms for providing efficient transistor functionality of an integrated circuit. In an embodiment, a transistor device comprises a first body of a high mobility semiconductor and a second body of a wide bandgap semiconductor. The first body adjoins each of, and is disposed between, the second body and a gate dielectric layer of the transistor. The second body extends between, and variously adjoins, each of a source of the transistor and a drain of the transistor. A location of the second body mitigates current leakage that might otherwise occur via the first body. In another embodiment, a mobility of the first body is equal to or greater than 100 cm2/V·s, wherein a bandgap of the second body is equal to or greater than 2.0 eV.

Abstract: Embodiments related to transistors having one or more non-planar transition metal dichalcogenide cladding layers, integrated circuits and systems incorporating such transistors, and methods for fabricating them are discussed.

Abstract: A memory device includes a first electrode, a non-volatile memory element having a first terminal and a second terminal, where the first terminal is coupled to the first electrode. The memory device further includes a selector having a first terminal, a second terminal and a sidewall between the first and second terminals, where the second terminal of the selector is coupled to the first terminal of the non-volatile memory element. A second electrode is coupled to the second terminal of the selector and a third electrode laterally adjacent to the sidewall of the selector.

Abstract: Techniques and mechanisms for providing a complementary metal-oxide-semiconductor (CMOS) circuit which includes a group III-nitride (III-N) material. In an embodiment, an n-type transistor of the CMOS circuit comprises structures which are variously disposed on a group III-N semiconductor material. The n-type transistor is coupled to a p-type transistor of the CMOS circuit, wherein a channel region of the p-type transistor comprises a group III-V semiconductor material. The channel region is configured to conduct current along a first direction, where a surface portion of the group III-N semiconductor material extends along a second direction perpendicular to the second direction. In another embodiment, the group III-N semiconductor material includes a gallium-nitride (GaN) compound, and the group III-V semiconductor material includes a nanopillar of an indium antimonide (InSb) compound.

Abstract: FETs including a gated oxide semiconductor spacer interfacing with a channel semiconductor. Transistors may incorporate a non-oxide channel semiconductor, and one or more oxide semiconductors disposed proximal to the transistor gate electrode and the source/drain semiconductor, or source/drain contact metal. In advantageous embodiments, the oxide semiconductor is to be gated by a voltage applied to the gate electrode (i.e., gate voltage) so as to switch the oxide semiconductor between insulating and semiconducting states in conjunction with gating the transistor's non-oxide channel semiconductor between on and off states.

Abstract: Embodiments of the present disclosure describe a non-planar gate thin film transistor. An integrated circuit may include a plurality of layers formed on a substrate, and the plurality of layers may include a first one of a source or drain, an inter-layer dielectric (ILD) formed on the first one of the source or drain, and a second one of the source or drain formed on the ILD. A semiconductive layer may be formed on a sidewall of the plurality of layers. A gate dielectric layer formed on the semiconductive layer, and a gate may be in contact with the gate dielectric layer.

Abstract: An apparatus including a transistor device including a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel includes a length dimension between source and drain that is greater than a length dimension of the gate electrode such that there is a passivated underlap between an edge of the gate electrode and an edge of the channel relative to each of the source and the drain. A method including forming a channel of a transistor device on a substrate; forming first and second passivation layers on a surface of substrate on opposite sides of the channel; forming a gate stack on the channel between first and second passivation layers; and forming a source on the substrate between the channel and the first passivation layer and a drain on the substrate between the channel and the second passivation layer.

Abstract: Deep gate-all-around semiconductor devices having germanium or group 111-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.

Abstract: Substrates, assemblies, and techniques for an apparatus, where the apparatus includes a gate, where the gate includes a first gate side and a second gate side opposite to the first gate side, a gate dielectric on the gate, where the gate dielectric includes a first gate dielectric side and a second gate dielectric side opposite to the first gate dielectric side, a first dielectric, where the first dielectric abuts the first gate side, the first gate dielectric side, the second gate side, and the second gate dielectric side, a channel, where the gate dielectric is between the channel and the gate, a source coupled with the channel, and a drain coupled with the channel, where the first dielectric abuts the source and the drain. In an example, the first dielectric and the gate dielectric help insulate the gate from the channel, the source, and the drain.

Abstract: Techniques are disclosed for forming transistor devices having reduced interfacial resistance in a local interconnect. The local interconnect can be a material having similar composition to that of the source/drain material. That composition can be a metal alloy of a group IV element such as nickel germanide. The local interconnect of the semiconductor integrated circuit can function in the absence of barrier and liner layers. The devices can be used on MOS transistors including PMOS transistors.

Abstract: Methods of selectively nitriding surfaces of semiconductor devices are disclosed. For example, a hardmask is formed on the top portion of the fins to create SOI structure. The hardmask may be formed by nitriding the top portion of the fin. In other embodiments, silicon nitride is grown on the top portion of the fin to form the hard masks. In another example, internal spacers are formed between adjacent nanowires in a gate-all-around structure. The internal spacers may be formed by nitriding the remaining interlayer material between the channel region and source and drain regions.

Abstract: Disclosed herein are quantum dot devices with gate interface materials, as well as related computing devices and methods. For example, a quantum dot device may include a quantum well stack, a gate interface material, and a high-k gate dielectric. The gate interface material may be disposed between the high-k gate dielectric and the quantum well stack.

Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a cap region on the substrate adjacent a second side of the semiconductor region, wherein the cap region comprises semiconductor material of a higher band gap than the semiconductor region, and a drain region comprising doped semiconductor material on the cap region. Other embodiments are also disclosed and claimed.