Patents by Inventor Vedvyas Shanbhogue

Vedvyas Shanbhogue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220197816
    Abstract: An embodiment of an integrated circuit may comprise, coupled to a core, hardware decompression accelerators, a compressed cache, a processor communicatively coupled to the hardware decompression accelerators and the compressed cache, and memory communicatively coupled to the processor, wherein the memory stores microcode instructions that when executed by the processor causes the processor to load a page table entry in response to an indication of a page fault, determine if the page table entry indicates that the page is to be decompressed on fault, and, if so determined, modify a first decompression work descriptor at a first address and a second decompression work descriptor at a second address based on information from the page table entry, and generate a first enqueue transaction to the hardware decompression accelerators with the first address of the first decompression work descriptor and a second enqueue transaction to the hardware decompression accelerators with the second address of the second decomp
    Type: Application
    Filed: December 22, 2020
    Publication date: June 23, 2022
    Applicant: Intel Corporation
    Inventors: George Powley, Vinodh Gopal, Vedvyas Shanbhogue
  • Publication number: 20220197813
    Abstract: Methods and apparatus relating to techniques for increasing per core memory bandwidth by using forget store operations are described. In an embodiment, a cache stores a buffer. Execution circuitry executes an instruction. The instruction causes one or more cachelines in the cache to be marked based on a start address for the buffer and a size of the buffer. A marked cacheline in the cache is to be prevented from being written back to memory. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 23, 2022
    Applicant: Intel Corporation
    Inventors: Jayesh Gaur, Adarsh Chauhan, Vinodh Gopal, Vedvyas Shanbhogue, Sreenivas Subramoney, Wajdi Feghali
  • Publication number: 20220197799
    Abstract: Methods and apparatus relating to an instruction and/or micro-architecture support for decompression on core are described. In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more load operations to fetch data into one or more cachelines of a cache of a processor core. Decompression Engine (DE) circuitry decompresses the fetched data from the one or more cachelines of the cache of the processor core in response to the second micro operation. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 23, 2022
    Applicant: Intel Corporation
    Inventors: Jayesh Gaur, Adarsh Chauhan, Vinodh Gopal, Vedvyas Shanbhogue, Sreenivas Subramoney, Wajdi Feghali
  • Publication number: 20220197793
    Abstract: An embodiment of an integrated circuit may comprise, coupled to a core, a hardware decompression accelerator, a compressed cache, a processor and communicatively coupled to the hardware decompression accelerator and the compressed cache, and memory and communicatively coupled to the processor, wherein the memory stores microcode instructions which when executed by the processor causes the processor to store a first address to a decompression work descriptor, retrieve a second address where a compressed page is stored in the compressed cache from the decompression work descriptor at the first address in response to an indication of a page fault, and send instructions to the hardware decompression accelerator to decompress the compressed page at the second address. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: December 22, 2020
    Publication date: June 23, 2022
    Applicant: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Jayesh Gaur, Wajdi K. Feghali, Vinodh Gopal, Utkarsh Kakaiya
  • Patent number: 11360910
    Abstract: A processor includes a processor core and a memory controller coupled to the processor core. The memory controller comprising a cryptographic engine to: detect, in a write request for a cache line, a key identifier (ID) within a physical address of a location in memory; determine that the key ID is a trust domain key ID of a plurality of key IDs; responsive to a determination that the key ID is the trust domain key ID, set an ownership bit of the cache line to indicate the cache line belongs to a trust domain; encrypt the cache line to generate encrypted data; determine a message authentication code (MAC) associated with the cache line; and write the encrypted data, the ownership bit, and the MAC of the cache line to the memory.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 14, 2022
    Assignee: INTEL CORPORATION
    Inventors: Siddhartha Chhabra, Vedvyas Shanbhogue, Ravi L. Sahita
  • Patent number: 11354128
    Abstract: In one embodiment, software executing on a data processing system that is capable of performing dynamic operational mode transitions can realize performance improvements by predicting transitions between modes and/or predicting aspects of a new operational mode. Such prediction can allow the processor to begin an early transition into the target mode. The mode transition prediction principles can be applied for various processor mode transitions including 64-bit to 32-bit mode transitions, interrupts, exceptions, traps, virtualization mode transfers, system management mode transfers, and/or secure execution mode transfers.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: June 7, 2022
    Assignee: Intel Corporation
    Inventors: Jason W. Brandt, Vedvyas Shanbhogue, Kameswar Subramaniam
  • Publication number: 20220171625
    Abstract: An apparatus and method for efficiently managing shadow stacks. For example, one embodiment of a processor comprises: a plurality of registers to store a plurality of shadow stack pointers (SSPs); event processing circuitry to select a first SSP of the plurality of SSPs from a first register of the plurality of registers responsive to receipt of a first event associated with a first event priority level, the first SSP usable to identify a top of a first shadow stack; verification and utilization checking circuitry to determine whether the first SSP has been previously verified, wherein if the first SSP has not been previously verified then initiating a set of atomic operations to verify the first SSP and confirm that the first SSP is not in use, the set of atomic operations using a locking operation to lock data until the set of atomic operations are complete.
    Type: Application
    Filed: February 1, 2022
    Publication date: June 2, 2022
    Inventors: Vedvyas SHANBHOGUE, Gilbert NEIGER, Deepak K. GUPTA, H. Peter ANVIN
  • Patent number: 11347680
    Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Stephen J. Robinson, Christopher D. Bryant, Jason W. Brandt
  • Patent number: 11347839
    Abstract: Various embodiments are generally directed to techniques for control flow protection with minimal performance overhead, such as by utilizing one or more micro-architectural optimizations to implement a shadow stack (SS) to verify a return address before returning from a function call, for instance. Some embodiments are particularly directed to a computing platform, such as an internet of things (IoT) platform, that overlaps or parallelizes one or more SS access operations with one or more data stack (DS) access operations.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 31, 2022
    Assignee: INTEL CORPORATION
    Inventors: Abhishek Basak, Ravi L. Sahita, Vedvyas Shanbhogue
  • Publication number: 20220147393
    Abstract: An embodiment of an apparatus comprises decode circuitry to decode a single instruction, the single instruction to include a field for an identifier of a first source operand, a field for an identifier of a destination operand, and a field for an opcode, the opcode to indicate execution circuitry is to program a user timer, and execution circuitry to execute the decoded instruction according to the opcode to retrieve timer program information from a location indicated by the first source operand, and program a user timer indicated by the destination operand based on the retrieved timer program information. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: March 25, 2021
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventors: Rajesh Sankaran, Gilbert Neiger, Vedvyas Shanbhogue, David Koufaty
  • Publication number: 20220138286
    Abstract: Systems, apparatuses and methods may provide for encryption based technology. Data may be encrypted locally with a graphics processor with encryption engines. The graphics processor components may be verified with a root-of-trust and based on collection of claims. The graphics processor may further be able to modify encrypted data from a non-pageable format to a pageable format. The graphics processor may further process data associated with a virtual machine based on a key that is known by the virtual machine and the graphics processor.
    Type: Application
    Filed: December 23, 2020
    Publication date: May 5, 2022
    Applicant: Intel Corporation
    Inventors: David Zage, Scott Janus, Ned M. Smith, Vidhya Krishnan, Siddhartha Chhabra, Rajesh Poornachandran, Tomer Levy, Julien Carreno, Ankur Shah, Ronald Silvas, Aravindh Anantaraman, David Puffer, Vedvyas Shanbhogue, David Cowperthwaite, Aditya Navale, Omer Ben-Shalom, Alex Nayshtut, Xiaoyu Ruan
  • Patent number: 11301309
    Abstract: Systems, methods, and apparatuses relating to processor non-write-back capabilities are described. In one embodiment, a processor includes a plurality of logical processors, a control register comprising a non-write-back lock disable bit, a cache shared by the plurality of logical processors, a bus to couple the cache to a memory to service a memory request for the memory from the plurality of logical processors, and a memory controller to disable a non-write-back lock access of the bus for a read-modify-write type of the memory request issued by a logical processor of the plurality of logical processors when the non-write-back lock disable bit is set to a first value, and implement the non-write-back lock access of the bus for the read-modify-write type of the memory request when the non-write-back lock disable bit is set to a second value.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: April 12, 2022
    Assignee: Intel Corporation
    Inventors: Hisham Shafi, Vedvyas Shanbhogue, Gilbert Neiger, James A. Coleman
  • Publication number: 20220100514
    Abstract: Techniques for processing loops are described. An exemplary apparatus at least includes decoder circuitry to decode a single instruction, the single instruction to include a field for an opcode, the opcode to indicate execution circuitry is to perform an operation to configure execution of one or more loops, wherein the one or more loops are to include a plurality of configuration instructions and instructions that are to use metadata generated by ones of the plurality of configuration instructions; and execution circuitry to perform the operation as indicated by the opcode.
    Type: Application
    Filed: December 26, 2020
    Publication date: March 31, 2022
    Inventors: Anant NORI, Shankar BALACHANDRAN, Sreenivas SUBRAMONEY, Joydeep RAKSHIT, Vedvyas SHANBHOGUE, Avishaii ABUHATZERA, Belliappa KUTTANNA
  • Publication number: 20220091992
    Abstract: Techniques and mechanisms for identifying tag information that describes data to be cached at a processor. In an embodiment, a memory controller services a memory access request from the processor, wherein the memory controller reads multiple chunks of data from a memory device, and determines first tag information which corresponds to the multiple chunks. One or more of the multiple chunks are sent to the processor in a response to the request. Based on the first tag information, the memory controller detects for a match—if any—between at least two tags. Where such a match is detected, the memory controller further indicates to the processor that second tag information corresponds to the one or more chunks. In another embodiment, the first tag information is more granular than the second tag information.
    Type: Application
    Filed: September 23, 2020
    Publication date: March 24, 2022
    Applicant: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Siddhartha Chhabra
  • Publication number: 20220091998
    Abstract: Technologies for secure device configuration and management include a computing device having an I/O device. A trusted agent of the computing device is trusted by a virtual machine monitor of the computing device. The trusted agent securely commands the I/O device to enter a trusted I/O mode, securely commands the I/O device to set a global lock on configuration registers, receives configuration data from the I/O device, and provides the configuration data to a trusted execution environment. In the trusted I/O mode, the I/O device rejects a configuration command if a configuration register associated with the configuration command is locked and the configuration command is not received from the trusted agent. The trusted agent may provide attestation information to the trusted execution environment. The trusted execution environment may verify the configuration data and the attestation information. Other embodiments are described and claimed.
    Type: Application
    Filed: December 6, 2021
    Publication date: March 24, 2022
    Applicant: Intel Corporation
    Inventors: Reshma Lal, Pradeep M. Pappachan, Luis Kida, Krystof Zmudzinski, Siddhartha Chhabra, Abhishek Basak, Alpa Narendra Trivedi, Anna Trikalinou, David M. Lee, Vedvyas Shanbhogue, Utkarsh Y. Kakaiya
  • Publication number: 20220058023
    Abstract: Systems, methods, and apparatuses relating to circuitry to implement individually revocable capabilities for enforcing temporal memory safety are described. In one embodiment, a hardware processor comprises an execution unit to execute an instruction to request access to a block of memory through a pointer to the block of memory, and a memory controller circuit to allow access to the block of memory when an allocated object tag in the pointer is validated with an allocated object tag in an entry of a capability table in memory that is indexed by an index value in the pointer, wherein the memory controller circuit is to clear the allocated object tag in the capability table when a corresponding object is deallocated.
    Type: Application
    Filed: November 2, 2021
    Publication date: February 24, 2022
    Inventors: Michael LEMAY, Vedvyas SHANBHOGUE, Deepak GUPTA, Ravi SAHITA, David M. DURHAM, Willem PINCKAERS, Enrico PERLA
  • Patent number: 11243769
    Abstract: An apparatus and method for efficiently managing shadow stacks.
    Type: Grant
    Filed: March 28, 2020
    Date of Patent: February 8, 2022
    Assignee: INTEL CORPORATION
    Inventors: Vedvyas Shanbhogue, Gilbert Neiger, Deepak K. Gupta, H. Peter Anvin
  • Patent number: 11243893
    Abstract: A processor or system includes a processor core to execute a set of instructions to determine that a memory encryption mode is enabled. The memory encryption mode is to cause data stored to memory to be encrypted and data retrieved from the memory to be decrypted. The processor core is further to determine that a debug mode has been enabled and, responsive to a determination that the debug mode has been enabled, generate a second encryption key different than a first encryption key employed before reboot of a computing system. The processor core is further to transmit the second encryption key to a cryptographic engine for use in encryption and decryption of the data according to the memory encryption mode.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: February 8, 2022
    Assignee: Intel Corporation
    Inventors: Jonathan Lutz, Reouven Elbaz, Jason W. Brandt, Hisham Shafi, Ittai Anati, Vedvyas Shanbhogue
  • Publication number: 20220027287
    Abstract: This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.
    Type: Application
    Filed: October 7, 2021
    Publication date: January 27, 2022
    Applicant: Intel Corporation
    Inventors: Ravi L. SAHITA, Gilbert NEIGER, Vedvyas SHANBHOGUE, David M. DURHAM, Andrew V. ANDERSON, David A. KOUFATY, Asit K. MALLICK, Arumugam THIYAGARAJAH, Barry E. HUNTLEY, Deepak K. GUPTA, Michael LEMAY, Joseph F. CIHULA, Baiju V. PATEL
  • Publication number: 20220019432
    Abstract: A processor includes an execution unit and a processing logic operatively coupled to the execution unit, the processing logic to: enter a first execution state and transition to a second execution state responsive to executing a control transfer instruction. Responsive to executing a target instruction of the control transfer instruction, the processing logic further transitions to the first execution state responsive to the target instruction being a control transfer termination instruction of a mode identical to a mode of the processing logic following the execution of the control transfer instruction; and raises an execution exception responsive to the target instruction being a control transfer termination instruction of a mode different than the mode of the processing logic following the execution of the control transfer instruction.
    Type: Application
    Filed: August 17, 2021
    Publication date: January 20, 2022
    Applicant: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Jason W. Brandt, Ravi L. Sahita, Xiaoning Li