Patents by Inventor Veeraraghavan Dhandapani
Veeraraghavan Dhandapani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7736957Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming an insulating layer over a sidewall of the gate electrode; defining source and drain regions in the semiconductor substrate adjacent to the insulating layer; implanting a dopant in the source and drain regions of the semiconductor substrate to form doped source and drain regions; forming a sidewall spacer adjacent to the insulating layer; forming a recess in the semiconductor substrate in the source and drain regions, wherein the recess extends directly underneath the spacer a predetermined distance from a channel regions; and forming a stressor material in the recess. The method allows the stressor material to be formed closer to a channel region, thus improving carrier mobility in the channel while not degrading short channel effects.Type: GrantFiled: May 31, 2007Date of Patent: June 15, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Paul A. Grudowski, Veeraraghavan Dhandapani, Darren V. Goedeke, Voon-Yew Thean, Stefan Zollner
-
Patent number: 7687354Abstract: In a semiconductor fabrication process, an epitaxial layer is formed overlying a substrate, wherein there is a lattice mismatch between the epitaxial layer and the substrate. A hard mask having an opening is formed overlying the epitaxial layer. A recess is formed through the epitaxial layer and into the substrate. The recess is substantially aligned to the opening in the hard mask. A channel region of a semiconductor device is formed in the recess.Type: GrantFiled: February 29, 2008Date of Patent: March 30, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Paul A. Grudowski, Veeraraghavan Dhandapani, Stefan Zollner
-
Patent number: 7645651Abstract: A method of forming a metal oxide semiconductor (MOS) device comprises defining an active area in an unstrained semiconductor layer structure, depositing a hard mask overlying the active area and a region outside of the active area, patterning the hard mask to expose the active area, selectively growing a strained semiconductor layer overlying the exposed active area, and forming a remainder of the MOS device. The active area includes a first doped region of first conductivity type and a second doped region of second conductivity type. The strained semiconductor layer provides a biaxially strained channel for the MOS device.Type: GrantFiled: December 6, 2007Date of Patent: January 12, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Xiaoqiu Huang, Veeraraghavan Dhandapani, Bich-Yen Nguyen, Amanda M. Kroll, Daniel T. Pham
-
Publication number: 20090221119Abstract: In a semiconductor fabrication process, an epitaxial layer is formed overlying a substrate, wherein there is a lattice mismatch between the epitaxial layer and the substrate. A hard mask having an opening is formed overlying the epitaxial layer. A recess is formed through the epitaxial layer and into the substrate. The recess is substantially aligned to the opening in the hard mask. A channel region of a semiconductor device is formed in the recess.Type: ApplicationFiled: February 29, 2008Publication date: September 3, 2009Inventors: Paul A. Grudowski, Veeraraghavan Dhandapani, Stefan Zollner
-
Publication number: 20090146180Abstract: A method of forming a metal oxide semiconductor (MOS) device comprises defining an active area in an unstrained semiconductor layer structure, depositing a hard mask overlying the active area and a region outside of the active area, patterning the hard mask to expose the active area, selectively growing a strained semiconductor layer overlying the exposed active area, and forming a remainder of the MOS device. The active area includes a first doped region of first conductivity type and a second doped region of second conductivity type. The strained semiconductor layer provides a biaxially strained channel for the MOS device.Type: ApplicationFiled: December 6, 2007Publication date: June 11, 2009Inventors: Xiaoqiu Huang, Veeraraghavan Dhandapani, Bich-Yen Nguyen, Amanda M. Kroll, Daniel T. Pham
-
Patent number: 7544997Abstract: A method for forming a semiconductor device includes forming a recess in a source region and a recess in a drain region of the semiconductor device. The method further includes forming a first semiconductor material layer in the recess in the source region and a second semiconductor material layer in the recess in the drain region, wherein each of the first semiconductor material layer and the second semiconductor material layer are formed using a stressor material having a first ratio of an atomic concentration of a first element and an atomic concentration of a second element, wherein the first element is silicon and a first level of concentration of a doping material. The method further includes forming additional semiconductor material layers overlying the first semiconductor material layer and the second semiconductor material layer that have a different ratio of the atomic concentration of the first element and the second element.Type: GrantFiled: February 16, 2007Date of Patent: June 9, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Da Zhang, Veeraraghavan Dhandapani, Darren V. Goedeke, Jill C. Hildreth
-
Publication number: 20080299724Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming an insulating layer over a sidewall of the gate electrode; defining source and drain regions in the semiconductor substrate adjacent to the insulating layer; implanting a dopant in the source and drain regions of the semiconductor substrate to form doped source and drain regions; forming a sidewall spacer adjacent to the insulating layer; forming a recess in the semiconductor substrate in the source and drain regions, wherein the recess extends directly underneath the spacer a predetermined distance from a channel regions; and forming a stressor material in the recess. The method allows the stressor material to be formed closer to a channel region, thus improving carrier mobility in the channel while not degrading short channel effects.Type: ApplicationFiled: May 31, 2007Publication date: December 4, 2008Inventors: Paul A. Grudowski, Veeraraghavan Dhandapani, Darren V. Goedeke, Voon-Yew Thean, Stefan Zollner
-
Publication number: 20080293192Abstract: A semiconductor device is formed in a semiconductor layer. A gate dielectric is formed over a top surface of the semiconductor layer. A gate stack is over the gate dielectric. A sidewall spacer is formed around the gate stack. Using the sidewall spacer as a mask, an implant is performed to form deep source/drain regions in the semiconductor layer. Silicon carbon regions are formed on the deep source/drain regions and a top surface of the gate stack. The silicon carbon regions are silicided with nickel.Type: ApplicationFiled: May 22, 2007Publication date: November 27, 2008Inventors: Stefan Zollner, Veeraraghavan Dhandapani, Paul A. Grudowski
-
Patent number: 7427549Abstract: Removing a portion of a structure in a semiconductor device to separate the structure. The structure has two portions of different heights. In one example, the structure is removed by forming a spacer over the lower portion adjacent to the sidewall of the higher portion. A second material is then formed on the structure outside of the spacer. The spacer is removed and the portion under the spacer is then removed to separate the structure at that location. In one embodiment, separate channel regions are implemented in the separated structures. In other embodiments, separate gate structures are implemented in the separated structures.Type: GrantFiled: March 31, 2006Date of Patent: September 23, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Leo Mathew, Ramachandran Muralidhar, Veeraraghavan Dhandapani
-
Patent number: 7416605Abstract: An anneal of an epitaxially grown crystalline semiconductor layer comprising a combination of group-IV elements. The layer contains at least one of the group of carbon and tin. The layer of epitaxially grown material is annealed at a temperature substantially in a range of 1,000 to 1,400 degrees Celsius for a period not to exceed 100 milliseconds within 10% of the peak temperature. The anneal is performed for example with a laser anneal or a flash lamp anneal. The limited-time anneal may improve carrier mobility of a transistor.Type: GrantFiled: January 8, 2007Date of Patent: August 26, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Stefan Zollner, Veeraraghavan Dhandapani, Paul A. Grudowski, Gregory S. Spencer
-
Publication number: 20080197412Abstract: A method for forming a semiconductor device includes forming a recess in a source region and a recess in a drain region of the semiconductor device. The method further includes forming a first semiconductor material layer in the recess in the source region and a second semiconductor material layer in the recess in the drain region, wherein each of the first semiconductor material layer and the second semiconductor material layer are formed using a stressor material having a first ratio of an atomic concentration of a first element and an atomic concentration of a second element, wherein the first element is silicon and a first level of concentration of a doping material. The method further includes forming additional semiconductor material layers overlying the first semiconductor material layer and the second semiconductor material layer that have a different ratio of the atomic concentration of the first element and the second element.Type: ApplicationFiled: February 16, 2007Publication date: August 21, 2008Inventors: Da Zhang, Veeraraghavan Dhandapani, Darren V. Goedeke, Jill C. Hildreth
-
Publication number: 20080163813Abstract: An anneal of an epitaxially grown crystalline semiconductor layer comprising a combination of group-IV elements. The layer contains at least one of the group of carbon and tin. The layer of epitaxially grown material is annealed at a temperature substantially in a range of 1,000 to 1,400 degrees Celsius for a period not to exceed 100 milliseconds within 10% of the peak temperature. The anneal is performed for example with a laser anneal or a flash lamp anneal. The limited-time anneal may improve carrier mobility of a transistor.Type: ApplicationFiled: January 8, 2007Publication date: July 10, 2008Inventors: Stefan Zollner, Veeraraghavan Dhandapani, Paul A. Grudowski, Gregory S. Spencer
-
Publication number: 20070238278Abstract: Removing a portion of a structure in a semiconductor device to separate the structure. The structure has two portions of different heights. In one example, the structure is removed by forming a spacer over the lower portion adjacent to the sidewall of the higher portion. A second material is then formed on the structure outside of the spacer. The spacer is removed and the portion under the spacer is then removed to separate the structure at that location. In one embodiment, separate channel regions are implemented in the separated structures. In other embodiments, separate gate structures are implemented in the separated structures.Type: ApplicationFiled: March 31, 2006Publication date: October 11, 2007Inventors: Leo Mathew, Ramachandran Muralidhar, Veeraraghavan Dhandapani