Patents by Inventor Venkata N.S.N. Rao

Venkata N.S.N. Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9564905
    Abstract: A method for clocking a physical layer (“PHY”) and a controller of a computing device, comprises the steps of: generating a reference clock signal; synchronizing a plurality of clock signals as a function of the reference clock signal; and clocking the controller and the PHY using the plurality of synchronized clock signals.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: February 7, 2017
    Assignee: SOCTRONICS, INC.
    Inventors: Prasad Chalasani, Venkata N. S. N. Rao
  • Patent number: 9467149
    Abstract: A distribution network for distributing clock and reset signals across an address macro has circuit blocks having dividers and counters, drivers connected in a balanced tree, and drivers connected in an unbalanced tree. The dividers and counters are synchronized relative to a clock signal. The drivers connected in the balanced tree distribute the clock signal synchronously to the circuit blocks. The drivers connected in the unbalanced tree distribute a reset signal to the circuit blocks. The clock signal is distributed via the balanced tree as a function of the reset signal.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: October 11, 2016
    Assignee: SOCTRONICS, INC.
    Inventors: Prasad Chalasani, Venkata N.S.N. Rao
  • Patent number: 9444463
    Abstract: A method for voltage level shifting comprises several steps. A data signal in a first voltage domain is received by a voltage level shifter. The received data signal is shifted to a second voltage domain by the voltage level shifter, where the voltage level shifter is configured as a function of the shifted data signal. The shifted data signal is outputted.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: September 13, 2016
    Assignee: Invecas, Inc.
    Inventor: Venkata N. S. N. Rao
  • Publication number: 20160246325
    Abstract: A method for clocking a physical layer (“PHY”) and a controller of a computing device, comprises the steps of: generating a reference clock signal; synchronizing a plurality of clock signals as a function of the reference clock signal; and clocking the controller and the PHY using the plurality of synchronized clock signals.
    Type: Application
    Filed: May 3, 2016
    Publication date: August 25, 2016
    Inventors: Prasad Chalasani, Venkata N.S.N. Rao
  • Publication number: 20160218717
    Abstract: A method for voltage level shifting comprises several steps. A data signal in a first voltage domain is received by a voltage level shifter. The received data signal is shifted to a second voltage domain by the voltage level shifter, where the voltage level shifter is configured as a function of the shifted data signal. The shifted data signal is outputted.
    Type: Application
    Filed: January 28, 2015
    Publication date: July 28, 2016
    Inventor: Venkata N.S.N. Rao
  • Patent number: 9349421
    Abstract: A data path interface for transferring data to a memory device, comprising: programmable delay units (“PDUs”), wherein data is received by the interface according to a first clock signal and wherein the PDUs apply delays to the received data; and align blocks, wherein the align blocks select certain ones of the delayed data as a function of the first clock signal and a second clock signal, and wherein the selected certain ones of the delayed data are processed for transmission to the memory device according to the second clock signal.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: May 24, 2016
    Assignee: SOCTRONICS, INC.
    Inventors: Venkata N. S. N. Rao, Prasad Chalasani
  • Patent number: 9337846
    Abstract: A method for detecting a receiver on a computer bus, comprises the steps of: applying a low voltage state on transmission lines of the computer bus using a voltage mode driver; applying a high voltage state on the transmission lines using the voltage mode driver; determining a voltage rate change for transmission voltages on the transmission lines; and determining the presence of the receiver on the computer bus as a function of the voltage rate change.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: May 10, 2016
    Assignee: SoCtronics, Inc.
    Inventor: Venkata N. S. N. Rao
  • Patent number: 9286260
    Abstract: A method for converting serial data having a certain word size to parallel data, comprises the steps of: generating segments from the serial data using serially-connected stages, wherein the segments have a predetermined bit size; storing each of the segments into a selectively turned-on flip-flop of a final stage, wherein the final stage is serially connected to the stages, wherein the final stage has a plurality of flip-flops and each of the flip-flops has a bit size equaling to the bit size of the segments; and outputting the stored segments in parallel from the final stage.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: March 15, 2016
    Assignee: SOCTRONICS, INC.
    Inventor: Venkata N. S. N. Rao
  • Publication number: 20150221350
    Abstract: A data path interface for transferring data to a memory device, comprising: programmable delay units (“PDUs”), wherein data is received by the interface according to a first clock signal and wherein the PDUs apply delays to the received data; and align blocks, wherein the align blocks select certain ones of the delayed data as a function of the first clock signal and a second clock signal, and wherein the selected certain ones of the delayed data are processed for transmission to the memory device according to the second clock signal.
    Type: Application
    Filed: February 3, 2014
    Publication date: August 6, 2015
    Applicant: Kool Chip, Inc.
    Inventors: Venkata N.S.N. Rao, Prasad Chalasani
  • Patent number: 8952737
    Abstract: A method for calibrating a delay locked loop (“DLL”) having a plurality of delay segments, comprises: determining segment delay values for the delay segments; calculating a full-cycle delay value for an input signal to the DLL; adjusting one or more of the segment delay values as a function of the full-cycle delay value to generate one or more adjusted delay values; and calculating weights for the delay segments as a function of the segment delay values, the full-cycle delay, and the one or more adjusted delay values, wherein the weights are used to calibrate the DLL.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: February 10, 2015
    Assignee: Kool Chip, Inc.
    Inventors: Kishore Mishra, Purna C. Mohanty, Venkata N. S. N. Rao
  • Publication number: 20140317434
    Abstract: A distribution network, comprises: circuit blocks having counters, wherein the counters are synchronized relative to an input signal; drivers connected in a balanced tree for distributing the input signal synchronously to the circuit blocks; and drivers connected in an unbalanced tree for distributing a reset signal to the circuit blocks, wherein the input signal is distributed via the balanced tree as a function of the reset signal.
    Type: Application
    Filed: January 31, 2014
    Publication date: October 23, 2014
    Applicant: Kool Chip, Inc.
    Inventors: Prasad Chalasani, Venkata N.S.N. Rao
  • Publication number: 20140317432
    Abstract: A method for detecting a receiver on a computer bus, comprises the steps of: applying a low voltage state on transmission lines of the computer bus using a voltage mode driver; applying a high voltage state on the transmission lines using the voltage mode driver; determining a voltage rate change for transmission voltages on the transmission lines; and determining the presence of the receiver on the computer bus as a function of the voltage rate change.
    Type: Application
    Filed: June 19, 2013
    Publication date: October 23, 2014
    Inventor: Venkata N.S.N. Rao
  • Publication number: 20140314190
    Abstract: A method for clocking a physical layer (“PHY”) and a controller of a computing device, comprises the steps of: generating a reference clock signal; synchronizing a plurality of clock signals as a function of the reference clock signal; and clocking the controller and the PHY using the plurality of synchronized clock signals.
    Type: Application
    Filed: October 29, 2013
    Publication date: October 23, 2014
    Applicant: Kool Chip, Inc.
    Inventors: Prasad Chalasani, Venkata N.S.N. Rao
  • Publication number: 20140312945
    Abstract: A delay locked loop, comprises: a phase detector, wherein the phase detector generates output signals as a function of a reference clock signal and a feedback clock signal; a charge pump, wherein the charge pump generates a charge pump voltage as a function of the output signals; a bias generation circuit, wherein the bias generation circuit generates biasing signals as a function of the charge pump voltage; and a delay chain, wherein the delay chain outputs one or more internal clock signals and the feedback clock signal as a function of the reference clock signal and the biasing signals.
    Type: Application
    Filed: June 4, 2013
    Publication date: October 23, 2014
    Inventors: Sharat Ippili, Venkata N.S.N. Rao, Prasad Chalasani
  • Publication number: 20140312946
    Abstract: A method for calibrating a delay locked loop (“DLL”) having a plurality of delay segments, comprises: determining segment delay values for the delay segments; calculating a full-cycle delay value for an input signal to the DLL; adjusting one or more of the segment delay values as a function of the full-cycle delay value to generate one or more adjusted delay values; and calculating weights for the delay segments as a function of the segment delay values, the full-cycle delay, and the one or more adjusted delay values, wherein the weights are used to calibrate the DLL.
    Type: Application
    Filed: October 29, 2013
    Publication date: October 23, 2014
    Applicant: Kool Chip, Inc.
    Inventors: Kishore Mishra, Purna C. Mohanty, Venkata N.S.N. Rao
  • Publication number: 20140298075
    Abstract: A method for converting serial data having a certain word size to parallel data, comprises the steps of: generating segments from the serial data using one or more serially-connected first stages, wherein the segments have a predetermined bit size; storing each of the segments into a selectively turned-on flip-flop of a final stage, wherein the final stage is serially connected to the first stages, wherein the final stage has a plurality of flip-flops and each of the flip-flops has a bit size equaling to the bit size of the segments; and outputting the stored segments in parallel from the final stage.
    Type: Application
    Filed: March 27, 2013
    Publication date: October 2, 2014
    Applicant: Kool Chip, Inc.
    Inventor: Venkata N.S.N. Rao
  • Patent number: 8669792
    Abstract: A driver comprises, an input block for receiving one or more data signals and one or more control signals; a data control block for processing the data signals and the control signals to determine one or more modified control signals, wherein the modified control signal is determined as a function of one or more de-emphasis signals, one or more pre-emphasis signals, and the control signals; and a driver block for receiving the modified control signals and generating one or more output data signals.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: March 11, 2014
    Assignee: Kool Chip, Inc.
    Inventor: Venkata N. S. N. Rao
  • Patent number: 8643516
    Abstract: A method for converting parallel data having a certain word size to serial data, comprises the steps of: loading a first segment of a word of the parallel data into a shift register having a first size, and inputting remaining segments of the word into two or more multiplexers connected in series for selecting a next segment of the word; selecting the next segment of the word to load into the shift register; shifting out the loaded segment of the word in the shift register as serial data output; loading the selected next segment of the word into the shift register; and repeating the selecting, shifting, and loading the next segment steps until all the remaining segments of the word have been shifted as serial data output.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: February 4, 2014
    Assignee: Kool Chip, Inc.
    Inventor: Venkata N. S. N. Rao
  • Publication number: 20130057321
    Abstract: A driver comprises, an input block for receiving one or more data signals and one or more control signals; a data control block for processing the data signals and the control signals to determine one or more modified control signals, wherein the modified control signal is determined as a function of one or more de-emphasis signals, one or more pre-emphasis signals, and the control signals; and a driver block for receiving the modified control signals and generating one or more output data signals.
    Type: Application
    Filed: November 2, 2012
    Publication date: March 7, 2013
    Applicant: Kool Chip, Inc.
    Inventor: Venkata N.S.N. Rao
  • Publication number: 20130009669
    Abstract: A differential mode driver for driving a differential signal, comprises, at least one unit cell, wherein each of the at least one unit cell comprises at least one resistor and at least one switch resistance and wherein the ratio of the resistances of the at least one resistor and the at least one switch resistance is greater than or equal to a predefined ratio.
    Type: Application
    Filed: September 2, 2011
    Publication date: January 10, 2013
    Applicant: KOOL CHIP, INC.
    Inventor: Venkata N.S.N. Rao