Patents by Inventor Venkataratna Subrahmanya Bharathi Akondy
Venkataratna Subrahmanya Bharathi Akondy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11901901Abstract: In described examples, a pulse width modulation (PWM) system includes an initiator and a receiver. The initiator includes an initiator counter and an initiator PWM signal generator. The initiator counter advances an initiator count in response to an initiator clock signal. The initiator PWM signal generator generates an initiator PWM signal in response to the initiator count. The receiver includes a receiver counter, a receiver PWM signal generator, and circuitry configured to reset the receiver count. The receiver counter advances a receiver count in response to a receiver clock signal. The receiver PWM signal generator generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset.Type: GrantFiled: January 17, 2023Date of Patent: February 13, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Venkataratna Subrahmanya Bharathi Akondy Raja Raghupathi, Sam Gnana Sabapathy
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Patent number: 11870465Abstract: An analog-to-digital converter (ADC) includes a modulator, an integrator circuit, and first and second differentiator circuits. The modulator has a modulator input and a modulator output. The modulator input is configured to receive an analog signal, and the modulator is configured to generate digital data on the modulator output. The integrator circuit has an integrator circuit input and an integrator output. The integrator input is coupled to the modulator output. The first differentiator circuit is coupled to the integrator output, and the first differentiator circuit is configured to be clocked with a first clock. The second differentiator circuit is coupled to the integrator output, and the second differentiator circuit configured to be clocked with a second clock. The second clock is out of phase with respect to the first clock.Type: GrantFiled: January 10, 2023Date of Patent: January 9, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Venkataratna Subrahmanya Bharathi Akondy Raja Raghupathi
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Patent number: 11689350Abstract: A system includes a first controller configured to transmit a synchronization signal to a second controller. The second controller is configured to produce a PWM signal. The system also includes a counter configured to provide a count for the second controller, where the second controller is configured to initiate rising edges and falling edges of the PWM signal based on the count from the counter. The second controller is also configured to measure an error between a time when the synchronization signal is received at the second controller and an expected time of receipt for the synchronization signal. The second controller is also configured to adjust a period of the counter based at least in part on the error.Type: GrantFiled: June 7, 2022Date of Patent: June 27, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Manish Bhardwaj, Venkataratna Subrahmanya Bharathi Akondy, Shamim Choudhury
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Publication number: 20230170883Abstract: In described examples, a pulse width modulation (PWM) system includes an initiator and a receiver. The initiator includes an initiator counter and an initiator PWM signal generator. The initiator counter advances an initiator count in response to an initiator clock signal. The initiator PWM signal generator generates an initiator PWM signal in response to the initiator count. The receiver includes a receiver counter, a receiver PWM signal generator, and circuitry configured to reset the receiver count. The receiver counter advances a receiver count in response to a receiver clock signal. The receiver PWM signal generator generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset.Type: ApplicationFiled: January 17, 2023Publication date: June 1, 2023Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Venkataratna Subrahmanya Bharathi Akondy Raja Raghupathi, Sam Gnana Sabapathy
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Patent number: 11558038Abstract: In described examples, a pulse width modulation (PWM) system includes an initiator and a receiver. The initiator includes an initiator counter and an initiator PWM signal generator. The initiator counter advances an initiator count in response to an initiator clock signal. The initiator PWM signal generator generates an initiator PWM signal in response to the initiator count. The receiver includes a receiver counter, a receiver PWM signal generator, and circuitry configured to reset the receiver count. The receiver counter advances a receiver count in response to a receiver clock signal. The receiver PWM signal generator generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset.Type: GrantFiled: February 28, 2022Date of Patent: January 17, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Venkataratna Subrahmanya Bharathi Akondy Raja Raghupathi, Sam Gnana Sabapathy
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Patent number: 11552648Abstract: An analog-to-digital converter (ADC) includes a modulator, an integrator circuit, and first and second differentiator circuits. The modulator has a modulator input and a modulator output. The modulator input is configured to receive an analog signal, and the modulator is configured to generate digital data on the modulator output. The integrator circuit has an integrator circuit input and an integrator output. The integrator input is coupled to the modulator output. The first differentiator circuit is coupled to the integrator output, and the first differentiator circuit is configured to be clocked with a first clock. The second differentiator circuit is coupled to the integrator output, and the second differentiator circuit configured to be clocked with a second clock. The second clock is out of phase with respect to the first clock.Type: GrantFiled: July 21, 2021Date of Patent: January 10, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Venkataratna Subrahmanya Bharathi Akondy Raja Raghupathi
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Publication number: 20220376884Abstract: A system includes a first controller configured to transmit a synchronization signal to a second controller. The second controller is configured to produce a PWM signal. The system also includes a counter configured to provide a count for the second controller, where the second controller is configured to initiate rising edges and falling edges of the PWM signal based on the count from the counter. The second controller is also configured to measure an error between a time when the synchronization signal is received at the second controller and an expected time of receipt for the synchronization signal. The second controller is also configured to adjust a period of the counter based at least in part on the error.Type: ApplicationFiled: June 7, 2022Publication date: November 24, 2022Inventors: Manish BHARDWAJ, Venkataratna Subrahmanya Bharathi AKONDY, Shamim CHOUDHURY
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Publication number: 20220271739Abstract: In described examples, a pulse width modulation (PWM) system includes an initiator and a receiver. The initiator includes an initiator counter and an initiator PWM signal generator. The initiator counter advances an initiator count in response to an initiator clock signal. The initiator PWM signal generator generates an initiator PWM signal in response to the initiator count. The receiver includes a receiver counter, a receiver PWM signal generator, and circuitry configured to reset the receiver count. The receiver counter advances a receiver count in response to a receiver clock signal. The receiver PWM signal generator generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset.Type: ApplicationFiled: February 28, 2022Publication date: August 25, 2022Inventors: Venkataratna Subrahmanya Bharathi Akondy Raja Raghupathi, Sam Gnana Sabapathy
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Publication number: 20220239312Abstract: An analog-to-digital converter (ADC) includes a modulator, an integrator circuit, and first and second differentiator circuits. The modulator has a modulator input and a modulator output. The modulator input is configured to receive an analog signal, and the modulator is configured to generate digital data on the modulator output. The integrator circuit has an integrator circuit input and an integrator output. The integrator input is coupled to the modulator output. The first differentiator circuit is coupled to the integrator output, and the first differentiator circuit is configured to be clocked with a first clock. The second differentiator circuit is coupled to the integrator output, and the second differentiator circuit configured to be clocked with a second clock. The second clock is out of phase with respect to the first clock.Type: ApplicationFiled: July 21, 2021Publication date: July 28, 2022Inventor: Venkataratna Subrahmanya Bharathi AKONDY RAJA RAGHUPATHI
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Patent number: 11356238Abstract: A system includes a first controller configured to transmit a synchronization signal to a second controller. The second controller is configured to produce a PWM signal. The system also includes a counter configured to provide a count for the second controller, where the second controller is configured to initiate rising edges and falling edges of the PWM signal based on the count from the counter. The second controller is also configured to measure an error between a time when the synchronization signal is received at the second controller and an expected time of receipt for the synchronization signal. The second controller is also configured to adjust a period of the counter based at least in part on the error.Type: GrantFiled: May 24, 2021Date of Patent: June 7, 2022Assignee: Texas Instruments IncorporatedInventors: Manish Bhardwaj, Venkataratna Subrahmanya Bharathi Akondy, Shamim Choudhury
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Patent number: 11343067Abstract: An asynchronous data capture device comprises an edge spread detector circuit, a clock generator, and a data sampling circuit. The edge spread detector circuit uses a first clock frequency that is a multiple of a second clock frequency, identifies transitions in a data stream transmitted to the device at the second clock frequency, and determines a sampling point based on the identified transitions. The clock generator adjusts a phase offset based on the sampling point and generates a clock signal having the second clock frequency and the adjusted phase offset. The data sampling circuit uses the second clock frequency and samples the data stream at the sampling point. In some implementations, the edge spread detector determines a sampling point that is isolated from the identified transitions, and the clock generator adjusts the phase offset to cause a rising edge at the sampling point.Type: GrantFiled: November 10, 2020Date of Patent: May 24, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Venkataratna Subrahmanya Bharathi Akondy Raja Raghupathi
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Patent number: 11264972Abstract: In described examples, a pulse width modulation (PWM) system includes an initiator and a receiver. The initiator includes an initiator counter and an initiator PWM signal generator. The initiator counter advances an initiator count in response to an initiator clock signal. The initiator PWM signal generator generates an initiator PWM signal in response to the initiator count. The receiver includes a receiver counter, a receiver PWM signal generator, and circuitry configured to reset the receiver count. The receiver counter advances a receiver count in response to a receiver clock signal. The receiver PWM signal generator generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset.Type: GrantFiled: December 23, 2020Date of Patent: March 1, 2022Assignee: Texas Instruments IncorporatedInventors: Venkataratna Subrahmanya Bharathi Akondy Raja Raghupathi, Sam Gnana Sabapathy
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Publication number: 20210336608Abstract: In described examples, a pulse width modulation (PWM) system includes an initiator and a receiver. The initiator includes an initiator counter and an initiator PWM signal generator. The initiator counter advances an initiator count in response to an initiator clock signal. The initiator PWM signal generator generates an initiator PWM signal in response to the initiator count. The receiver includes a receiver counter, a receiver PWM signal generator, and circuitry configured to reset the receiver count. The receiver counter advances a receiver count in response to a receiver clock signal. The receiver PWM signal generator generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset.Type: ApplicationFiled: December 23, 2020Publication date: October 28, 2021Inventors: Venkataratna Subrahmanya Bharathi Akondy Raja Raghupathi, Sam Gnana Sabapathy
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Publication number: 20210058226Abstract: An asynchronous data capture device comprises an edge spread detector circuit, a clock generator, and a data sampling circuit. The edge spread detector circuit uses a first clock frequency that is a multiple of a second clock frequency, identifies transitions in a data stream transmitted to the device at the second clock frequency, and determines a sampling point based on the identified transitions. The clock generator adjusts a phase offset based on the sampling point and generates a clock signal having the second clock frequency and the adjusted phase offset. The data sampling circuit uses the second clock frequency and samples the data stream at the sampling point. In some implementations, the edge spread detector determines a sampling point that is isolated from the identified transitions, and the clock generator adjusts the phase offset to cause a rising edge at the sampling point.Type: ApplicationFiled: November 10, 2020Publication date: February 25, 2021Inventor: Venkataratna Subrahmanya Bharathi AKONDY RAJA RAGHUPATHI
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Patent number: 10862666Abstract: An asynchronous data capture device comprises an edge spread detector circuit, a clock generator, and a data sampling circuit. The edge spread detector circuit uses a first clock frequency that is a multiple of a second clock frequency, identifies transitions in a data stream transmitted to the device at the second clock frequency, and determines a sampling point based on the identified transitions. The clock generator adjusts a phase offset based on the sampling point and generates a clock signal having the second clock frequency and the adjusted phase offset. The data sampling circuit uses the second clock frequency and samples the data stream at the sampling point. In some implementations, the edge spread detector determines a sampling point that is isolated from the identified transitions, and the clock generator adjusts the phase offset to cause a rising edge at the sampling point.Type: GrantFiled: June 28, 2019Date of Patent: December 8, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Venkataratna Subrahmanya Bharathi Akondy Raja Raghupathi
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Publication number: 20200228304Abstract: An asynchronous data capture device comprises an edge spread detector circuit, a clock generator, and a data sampling circuit. The edge spread detector circuit uses a first clock frequency that is a multiple of a second clock frequency, identifies transitions in a data stream transmitted to the device at the second clock frequency, and determines a sampling point based on the identified transitions. The clock generator adjusts a phase offset based on the sampling point and generates a clock signal having the second clock frequency and the adjusted phase offset. The data sampling circuit uses the second clock frequency and samples the data stream at the sampling point. In some implementations, the edge spread detector determines a sampling point that is isolated from the identified transitions, and the clock generator adjusts the phase offset to cause a rising edge at the sampling point.Type: ApplicationFiled: June 28, 2019Publication date: July 16, 2020Inventor: Venkataratna Subrahmanya Bharathi AKONDY RAJA RAGHUPATHI