Abstract: Various embodiments of the present disclosure relate to conditional branch instructions to support software pipelining techniques. In an example embodiment, a system including instruction fetch circuitry, decoder circuitry, and conditional branch circuitry is provided. The instruction fetch circuitry is configured to fetch a conditional branch instruction from memory and provide the instruction to the decoder circuitry. The instruction includes an iteration count and multiple branch destinations. The branch destinations include two or more branch destinations corresponding to conditions against which the conditional branch circuitry evaluates the iteration count.

Abstract: Systems and methods provide for inherited access permissions, thereby facilitating read and write access by called contexts. Hardware logic may enforce access permissions in the system. When a processor core executes code associated with a first context, the processor core generates a first hardware signal identifying the first context. The processor core may then switch from the first context to the second context due to the first context calling the second context. The processor core may then generate a second hardware signal identifying the calling (first) context, and then the first hardware signal identifies the called (second) context. The hardware logic that enforces the access permissions may then determine that the second context is being called and that the second context includes either direct access permissions or inherited access permissions associated with the calling (first) context.

Abstract: An example apparatus includes: address generation circuitry configured to generate a first address associated with a first packet, a second address associated with a second packet, and a third address associated with a third packet, wherein: the first packet includes a branch instruction; the branch instruction includes a first field that specifies a branch target, and a second field that is different from the first field; and the third packet includes the branch target of the branch instruction; buffer circuitry configured to receive the first packet, the second packet, and the third packet; decoder circuitry coupled to the buffer circuitry, the decoder circuitry configured to decode the first packet, the second packet, and the third packet; discontinuity controller circuitry coupled to the buffer circuitry and the decoder circuitry and configured to determine whether to cause the address generation circuitry to generate the second address.

Abstract: In described examples, an integrated circuit (IC) includes a memory and a processor coupled to the memory. The processor is configured to execute a discontinuity instruction, which specifies a memory address, to transition from executing according to a first stack pointer to executing according to a second stack pointer. The first stack pointer is copied from an active stack register to an inactive first stack pointer register. The processor determines whether the specified memory address stores a stack entry instruction that corresponds to the discontinuity instruction. If it does, the second stack pointer is copied from the inactive second stack pointer register to the active stack register, and the processor executes the stack entry instruction and begins execution according to the second stack pointer.

Abstract: Various embodiments include systems and methods to provide deterministic execution times for computer processors. In one example, a hardware module may include hardware logic, which is configured to track a value stored in a counter. The hardware module may detect a read or write access request from a processor, determine whether the value stored in the counter has reached a specified value, and then stall the processor using a hardware signal in response thereto. Once the counter reaches the specified value, the hardware logic may then un-stalls the processor using the hardware signal.

Abstract: In described examples, a circuit device includes a memory having a set of memory ranges and a processor device coupled to the memory. The processor device is configured to fetch programmable instructions from the memory, and configured to determine memory access and execution permissions for the programmable instructions. Permissions are determined responsive to a set of a set of access protection registers (APRs) and a set of LINKs. The APRs each specify permissions for a respective associated memory range. The LINKs are each associated with a respective subset of the APRs. Each of the APRs specifies access protection responsive to each LINK. Each of the programmable instructions corresponds to the APR (source APR) associated with a memory range in which the programmable instruction is stored, and corresponds to the LINK (source LINK) associated with the respective source APR.

Abstract: In described examples, a circuit device includes a memory having a set of memory ranges, a logic circuit, access protection registers (APRs), ZONE debug permission registers, and a processor coupled to the memory. Each APR stores memory access permissions for an associated memory range. Each ZONE debug permission register stores debug permissions for a ZONE. Each ZONE is associated with a subset of the APRs so that each APR is associated with one ZONE. The processor executes a debug instruction to control the circuit device as follows. An APR associated with a memory address in the debug instruction provides a first permission to a first logic circuit input. The ZONE debug permission registers provide a second permission responsive to a credential to a second logic circuit input. The processor performs a debug action responsive to the debug instruction and a logic circuit output.

Abstract: Systems and methods may include bus monitoring hardware logic, where that bus monitoring hardware logic may monitor signals on one or more buses of processing unit, such as a central processing unit (CPU). Security logic may associate portions of code with code segregation units, such as links, stacks, and zones. Gating logic in the bus monitoring hardware logic may then enable or disable a monitoring function for a read or write access request based upon a link, stack, or zone identity associated with the piece of code making the read or write access request.

Abstract: Various embodiments of the present disclosure relate to the conditional execution of program code. In an example embodiment, a system including instruction fetch circuitry, decoder circuitry, and condition aggregation circuitry is provided. The instruction fetch circuitry is configured to fetch a conditional branch instruction (CBI) from memory which identifies multiple register locations and a condition aggregation operation. The condition aggregation operation is representative of an instruction which identifies multiple conditions to be checked. The instruction fetch circuitry provides the CBI to the decoder circuitry. In response, the decoder circuitry is configured to cause the condition aggregation circuitry to perform the multiple conditions checks with respect to values stored in the multiple register locations.

Abstract: Disclosed herein are methods for chromatography, including cleaning methods for chromatography medium that make use of a linear salt gradient. The disclosed methods may be used for frontal chromatography operations and for cleaning frontal chromatography media for reuse in biologics manufacturing.

Abstract: Various embodiments of the present disclosure relate to the conditional execution of program code. In an example embodiment, a system including instruction fetch circuitry, decoder circuitry, and multi-condition branch circuitry is provided. The instruction fetch circuitry is configured to fetch a multi-condition branch instruction (MCBI) from memory. The MCBI identifies multiple status registers and multiple branch destinations. The multiple status registers of the MCBI are representative of registers which hold results of multiple condition evaluations, such that each status register corresponds to a different one of the multiple condition evaluations. Similarly, the multiple branch destinations of the MCBI also correspond to a different one of the multiple condition evaluations. The instruction fetch circuitry provides the MCBI to the decoder circuitry. In response, the decoder circuitry is configured to cause the multi-condition branch circuitry to execute the multi-condition branch instruction.

Abstract: Methods, apparatus, systems, and articles of manufacture are described to facilitate unaligned byte stream operations. An example apparatus includes a register including a first portion and a second portion; and a decoder to, responsive to obtaining an instruction, move at least some data from the first portion of the register to the second portion of the register based on an address identified in the instruction; an interface to cause a multiple-byte read to access data from an aligned address of memory; and the decoder to store the accessed data into the first portion of the register based on the address identified in the instruction.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed for real-time trip sequence detection for cascaded trip events. An example integrated circuit device includes trip detector circuitry, a first counter, a first memory, a second counter, a second memory, and control circuitry in communication with the trip detector circuitry, the control circuitry to, in response to a first trigger detected by the fault detector circuit, store a value of the first counter in the first memory, and in response to a second trigger detected by the fault detector circuit, store a value of the second counter in the second memory. The trip detector circuitry will continue the same detection, identification and counter storage logic for the subsequent triggers limited only by the available storage capacity.

Abstract: An example apparatus includes example packet decode circuitry to decode an instruction packet for programmable circuitry into at least one instruction. Additionally, the example apparatus includes example instruction mapping circuitry to disregard a pad instruction included in the at least one instruction, the pad instruction having not been assigned to any functional unit of the programmable circuitry.

Abstract: Methods and systems configured for fast failover in ISP peering are disclosed herein. One method comprises: establishing a fault detection protocol session between a first router and a second router, the first and second routers being computing network peers; the first router responding to a data communication connection between the first router and a first provider edge router going down by altering a status of the fault detection protocol session to a changed status; and the second router responding to the changed status of the fault detection protocol session by rerouting traffic served by the first provider edge router to a second provider edge router.

Abstract: A processor with instruction storage configured to store processor instructions, data storage configured to store processor data representing an array, the array including plural data elements, a controller, and an instruction pipeline. The instruction pipeline includes: a load stage circuit configured to load an array element from the data storage, a compare stage circuit configured to compare the array element to a reference value, a store stage circuit configured to store a set of results that includes a result of the comparison of the array element to the reference value, and a loop hit detect stage circuit configured to determine whether any of the set of results is associated with a hit on the reference value.

Abstract: A processor with instruction storage configured to store processor instructions, data storage configured to store processor data representing an array, the array including plural data elements, a controller, and an instruction pipeline. The instruction pipeline includes: a load stage circuit configured to load an array element from the data storage, a compare stage circuit configured to compare the array element to a reference value, a store stage circuit configured to store a set of results that includes a result of the comparison of the array element to the reference value, and a loop hit detect stage circuit configured to determine whether any of the set of results is associated with a hit on the reference value.

Abstract: A processor with instruction storage configured to store processor instructions, data storage configured to store processor data representing an array, the array including plural data elements, a controller, and an instruction pipeline. The instruction pipeline includes: a load stage circuit configured to load an array element from the data storage, a compare stage circuit configured to compare the array element to a reference value, a store stage circuit configured to store a set of results that includes a result of the comparison of the array element to the reference value, and a loop hit detect stage circuit configured to determine whether any of the set of results is associated with a hit on the reference value.

Abstract: The disclosure provides a method of producing etanercept from Chinese hamster ovary cells (CHO), the method comprising running an N-1 bioreactor system using a recirculating tangential flow filtration (RTF) or alternating tangential flow filtration (ATF) cell retention device under conditions that maintain a cell aggregate size of at least 20 ?m, before running an N production bioreactor.

Abstract: Automated systems and methods for low-pH viral inactivation include adding an elution pool to a first vessel with an acid. Once first vessel pH probes measure sufficiently low pH, the pool is transferred to a second vessel, where the pH is checked again, and the pool is held for a time sufficient to reduce virus concentration to a safe level, and neutralized, filtered, and transferred to a third vessel. Meanwhile, the first vessel is filled with a known-pH buffer, which is checked against readings from first vessel pH probes to determine whether recalibration is needed. After the pool is transferred to the third vessel, the second vessel is filled with a known—pH buffer, which is checked against readings from second vessel pH probes to determine whether recalibration is needed. The process repeats when the known-pH buffer is dumped and a new elution pool is added to the first vessel.