Patents by Inventor Venkatesh Natarajan

Venkatesh Natarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240083972
    Abstract: The disclosure provides a method of producing etanercept from Chinese hamster ovary cells (CHO), the method comprising running an N-1 bioreactor system using a recirculating tangential flow filtration (RTF) or alternating tangential flow filtration (ATF) cell retention device under conditions that maintain a cell aggregate size of at least 20 ?m, before running an N production bioreactor.
    Type: Application
    Filed: December 21, 2021
    Publication date: March 14, 2024
    Applicant: AMGEN INC.
    Inventors: Eliyahu Kraus, Venkatesh Natarajan, Ritsdeliz Perez Rodriguez, Omar Cruz Nieves
  • Publication number: 20230416667
    Abstract: Automated systems and methods for low-pH viral inactivation include adding an elution pool to a first vessel with an acid. Once first vessel pH probes measure sufficiently low pH, the pool is transferred to a second vessel, where the pH is checked again, and the pool is held for a time sufficient to reduce virus concentration to a safe level, and neutralized, filtered, and transferred to a third vessel. Meanwhile, the first vessel is filled with a known-pH buffer, which is checked against readings from first vessel pH probes to determine whether recalibration is needed. After the pool is transferred to the third vessel, the second vessel is filled with a known—pH buffer, which is checked against readings from second vessel pH probes to determine whether recalibration is needed. The process repeats when the known-pH buffer is dumped and a new elution pool is added to the first vessel.
    Type: Application
    Filed: November 9, 2021
    Publication date: December 28, 2023
    Inventors: Venkatesh Natarajan, Marco DeLiso, Jeremy Aaron Bezaire, Andrew Cavigli, Jeremy S. Conner, Jon Hunter, Sidney Pehrson, Sarah Whetstone
  • Patent number: 11804983
    Abstract: One embodiment provides a system which facilitates scaling of routing in an EVPN. During operation, the system determines, in an Ethernet Virtual Private Network (EVPN), a plurality of virtual tunnel endpoints (VTEPs) coupled to a plurality of subnets, wherein a respective subnet includes one or more hosts, wherein a first VTEP is configured with a first number of host routes for a first subnet coupled to a second VTEP, and wherein each of the first number of host routes corresponds to a host residing in the first subnet. Responsive to detecting that a total number of routes configured on the first VTEP exceeds a first predetermined threshold, the system aggregates the first number of host routes by replacing the first number of host routes with a first prefix route which indicates the first subnet.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: October 31, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Venkatesh Natarajan, Badrish Adiga H R
  • Patent number: 11733969
    Abstract: In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: August 22, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Prasanth Viswanathan Pillai, Richard Mark Poley, Venkatesh Natarajan, Alexander Tessarolo
  • Publication number: 20230221959
    Abstract: A processor is provided and includes a core that is configured to perform a decode operation on a multi-instruction packet comprising multiple instructions. The decode operation includes receiving the multi-instruction packet that includes first and second instructions. The first instruction includes a primary portion at a fixed first location and a secondary portion. The second instruction includes a primary portion at a fixed second location between the primary portion of the first instruction and the secondary portion of the first instruction. An operational code portion of the primary portion of each of the first and second instructions is accessed and decoded. An instruction packet including the primary and secondary portions of the first instruction is created, and a second instruction packet including the primary portion of the second instruction is created. The first and second instructions packets are dispatched to respective first and second functional units.
    Type: Application
    Filed: February 27, 2023
    Publication date: July 13, 2023
    Inventors: Saya Goud Langadi, Venkatesh Natarajan, Alexander Tessarolo
  • Patent number: 11656964
    Abstract: A processor includes a central processing unit (CPU) and diagnostic monitoring circuitry. The diagnostic monitoring circuitry is coupled to the CPU. The diagnostic monitoring circuitry includes a monitoring and cyclic redundancy check (CRC) computation unit. The monitoring and CRC computation unit is configured to detect execution of a diagnostic program by the CPU, and to compute a plurality of CRC values. Each of CRC values corresponds to processor values retrieved from a given register of the CPU or from a bus coupling the CPU to a memory and peripheral subsystem while the CPU executes the diagnostic program.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: May 23, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Venkatesh Natarajan, Karthikeyan Rajamanickam
  • Patent number: 11646991
    Abstract: One aspect provides a method and system for managing address resolution requests in a network. During operation, a gateway of the network advertises a route for sending address resolution requests and determines whether a cached entry corresponding to an address resolution request received via the route exists in a neighbor table. In response to determining that the cached entry exists, the gateway responds to the address resolution request based on the cached entry; in response to determining that the cached entry does not exist, the gateway replicates the address resolution request to edge devices in the network, thereby facilitating discovery of a target host corresponding to the address resolution request.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: May 9, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Ankit Kumar Sinha, Saumya Dikshit, Vinayak Joshi, Venkatesh Natarajan
  • Patent number: 11593110
    Abstract: A processor is provided and includes a core that is configured to perform a decode operation on a multi-instruction packet comprising multiple instructions. The decode operation includes receiving the multi-instruction packet that includes first and second instructions. The first instruction includes a primary portion at a fixed first location and a secondary portion. The second instruction includes a primary portion at a fixed second location between the primary portion of the first instruction and the secondary portion of the first instruction. An operational code portion of the primary portion of each of the first and second instructions is accessed and decoded. An instruction packet including the primary and secondary portions of the first instruction is created, and a second instruction packet including the primary portion of the second instruction is created. The first and second instructions packets are dispatched to respective first and second functional units.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: February 28, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Saya Goud Langadi, Venkatesh Natarajan, Alexander Tessarolo
  • Publication number: 20220385620
    Abstract: One aspect provides a method and system for managing address resolution requests in a network. During operation, a gateway of the network advertises a route for sending address resolution requests and determines whether a cached entry corresponding to an address resolution request received via the route exists in a neighbor table. In response to determining that the cached entry exists, the gateway responds to the address resolution request based on the cached entry; in response to determining that the cached entry does not exist, the gateway replicates the address resolution request to edge devices in the network, thereby facilitating discovery of a target host corresponding to the address resolution request.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 1, 2022
    Inventors: Ankit Kumar Sinha, Saumya Dikshit, Vinayak Joshi, Venkatesh Natarajan
  • Patent number: 11398971
    Abstract: One embodiment provides a system and method for managing, at a network node, a data structure indicating neighbor node address information. During operation, the system can determine, based on a media access control (MAC) address or an Internet protocol (IP) address associated with an entry in the data structure, a type of the entry, and set a timeout value for the entry based on the determined type. In response to detecting that an entry corresponding to the MAC address expires in a MAC table maintained by the network node, the system can identify an interface on the network node to which a neighbor associated with the MAC address was previously coupled and transmit a unicast neighbor-probe packet on the identified interface to determine a connection status of the neighbor.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: July 26, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Badrish Adiga H R, Venkatesh Natarajan
  • Publication number: 20220231880
    Abstract: One embodiment provides a system which facilitates scaling of routing in an EVPN. During operation, the system determines, in an Ethernet Virtual Private Network (EVPN), a plurality of virtual tunnel endpoints (VTEPs) coupled to a plurality of subnets, wherein a respective subnet includes one or more hosts, wherein a first VTEP is configured with a first number of host routes for a first subnet coupled to a second VTEP, and wherein each of the first number of host routes corresponds to a host residing in the first subnet. Responsive to detecting that a total number of routes configured on the first VTEP exceeds a first predetermined threshold, the system aggregates the first number of host routes by replacing the first number of host routes with a first prefix route which indicates the first subnet.
    Type: Application
    Filed: January 15, 2021
    Publication date: July 21, 2022
    Inventors: Venkatesh Natarajan, Badrish Adiga H R
  • Publication number: 20220224626
    Abstract: One embodiment provides a system and method for managing, at a network node, a data structure indicating neighbor node address information. During operation, the system can determine, based on a media access control (MAC) address or an Internet protocol (IP) address associated with an entry in the data structure, a type of the entry, and set a timeout value for the entry based on the determined type. In response to detecting that an entry corresponding to the MAC address expires in a MAC table maintained by the network node, the system can identify an interface on the network node to which a neighbor associated with the MAC address was previously coupled and transmit a unicast neighbor-probe packet on the identified interface to determine a connection status of the neighbor.
    Type: Application
    Filed: January 12, 2021
    Publication date: July 14, 2022
    Inventors: Badrish Adiga H R, Venkatesh Natarajan
  • Publication number: 20220214880
    Abstract: A processor is provided and includes a core that is configured to perform a decode operation on a multi-instruction packet comprising multiple instructions. The decode operation includes receiving the multi-instruction packet that includes first and second instructions. The first instruction includes a primary portion at a fixed first location and a secondary portion. The second instruction includes a primary portion at a fixed second location between the primary portion of the first instruction and the secondary portion of the first instruction. An operational code portion of the primary portion of each of the first and second instructions is accessed and decoded. An instruction packet including the primary and secondary portions of the first instruction is created, and a second instruction packet including the primary portion of the second instruction is created. The first and second instructions packets are dispatched to respective first and second functional units.
    Type: Application
    Filed: January 7, 2021
    Publication date: July 7, 2022
    Inventors: Saya Goud Langadi, Venkatesh Natarajan, Alexander Tessarolo
  • Publication number: 20210342120
    Abstract: In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.
    Type: Application
    Filed: July 19, 2021
    Publication date: November 4, 2021
    Inventors: Prasanth Viswanathan Pillai, Richard Mark Poley, Venkatesh Natarajan, Alexander Tessarolo
  • Patent number: 11147006
    Abstract: Techniques for establishing and controlling information sharing via a dynamic wireless mesh network for a group of vehicles comprise determining a set of communication parameters for the group of vehicles and, based on the set of communication parameters, establishing the dynamic wireless mesh network for the group of vehicles, wherein each vehicle in the group of vehicles is a node in the dynamic wireless mesh network, determining a set of routing rules for the dynamic wireless mesh network, controlling information sharing between the group of vehicles through the dynamic wireless mesh network using the set of routing rules, and selectively adjusting the set of routing rules in response to changes in the set of communication parameters.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: October 12, 2021
    Assignee: FCA US LLC
    Inventors: Gunmeet Sandhu, David M Caranci, Craig D Conkling, Venkatesh Natarajan, Steven G Malson, Michael J Minewiser
  • Patent number: 11099815
    Abstract: In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: August 24, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Prasanth Viswanathan Pillai, Richard Mark Poley, Venkatesh Natarajan, Alexander Tessarolo
  • Patent number: 11061873
    Abstract: Systems and methods for normalizing and searching electronic data, such as chemical material property data, are disclosed. In one embodiment, a method includes receiving electronic data from a source. The electronic data is formatted in a source format. The method further includes converting the source data into a normalized format, and storing normalized electronic data in levels of a nested model. The method further includes receiving a search or browse query directed toward normalized properties in a first level of the nested model or a second level of the nested model, in any non-hierarchical order. The method also includes searching the nested model and causing for display on an electronic display one or more entities satisfying the query and maintaining the integrity of all parameters of the query across all selected properties queried in any non-hierarchical order.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: July 13, 2021
    Assignee: ELSEVIER, INC.
    Inventors: Venkatesh Natarajan, Yusufee Nathani, Avin Sijariya, Chi Yeung Cheung
  • Publication number: 20210022064
    Abstract: Techniques for establishing and controlling information sharing via a dynamic wireless mesh network for a group of vehicles comprise determining a set of communication parameters for the group of vehicles and, based on the set of communication parameters, establishing the dynamic wireless mesh network for the group of vehicles, wherein each vehicle in the group of vehicles is a node in the dynamic wireless mesh network, determining a set of routing rules for the dynamic wireless mesh network, controlling information sharing between the group of vehicles through the dynamic wireless mesh network using the set of routing rules, and selectively adjusting the set of routing rules in response to changes in the set of communication parameters.
    Type: Application
    Filed: July 15, 2019
    Publication date: January 21, 2021
    Inventors: Gunmeet Sandhu, David M. Caranci, Craig D. Conkling, Venkatesh Natarajan, Steven G. Malson, Michael J. Minewiser
  • Publication number: 20210004306
    Abstract: A processor includes a central processing unit (CPU) and diagnostic monitoring circuitry. The diagnostic monitoring circuitry is coupled to the CPU. The diagnostic monitoring circuitry includes a monitoring and cyclic redundancy check (CRC) computation unit. The monitoring and CRC computation unit is configured to detect execution of a diagnostic program by the CPU, and to compute a plurality of CRC values. Each of CRC values corresponds to processor values retrieved from a given register of the CPU or from a bus coupling the CPU to a memory and peripheral subsystem while the CPU executes the diagnostic program.
    Type: Application
    Filed: September 22, 2020
    Publication date: January 7, 2021
    Inventors: Venkatesh NATARAJAN, Karthikeyan RAJAMANICKAM
  • Publication number: 20200394019
    Abstract: In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.
    Type: Application
    Filed: July 21, 2020
    Publication date: December 17, 2020
    Inventors: Prasanth Viswanathan Pillai, Richard Mark Poley, Venkatesh Natarajan, Alexander Tessarolo