Patents by Inventor Venkatesh Prasad Ramachandra
Venkatesh Prasad Ramachandra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071519Abstract: The disclosure provides circuits and methods for increasing NAND input/output (I/O) bandwidth during read/write operations. The method includes transmitting a clock signal between a controller I/O circuit and a memory I/O circuit along a read enable bus, transmitting 8 bits of data along an I/O bus, and transmitting 2 bits of data along a data strobe signal (DQS) bus. Transmitting 2 bits of data along the DQS bus includes transmitting a first DQS data signal along the DQS bus and transmitting a first inverse DQS data signal along the DQS bus.Type: ApplicationFiled: August 29, 2022Publication date: February 29, 2024Inventors: TIANYU TANG, Venkatesh Prasad Ramachandra, Siddhesh Darne
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Patent number: 11869619Abstract: Systems and methods are provided that combine a write duty cycle adjuster with write training to reduce detection and duty cycle errors in memory devices. Various embodiments herein perform write duty cycle adjuster operations to adjust a duty cycle of a clock signal that coordinates a data signal with a data operation on the memory device based on an error in the duty cycle, and performs write training operations to detect a skew between the data signal and the clock signal and adjust a sampling transition of the duty cycle of the clock signal to align with a valid data window of the data signal.Type: GrantFiled: May 31, 2022Date of Patent: January 9, 2024Assignee: SANDISK TECHNOLOGIES LLCInventors: Jang Woo Lee, Srinivas Rajendra, Anil Pai, Venkatesh Prasad Ramachandra
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Publication number: 20230395108Abstract: Systems and methods disclosed herein provide for selectively activating or deactivating one or more memory of a memory array, such that related data path logic of deactivated memory dies neither detects nor processes control signals or data signals for data operations. Examples of the systems and methods provided herein operate to detect a first enable signal at a memory die and detect a first data signal on input/output (I/O) receivers of the memory die. Responsive to detecting at least the first enable signal, a bit value encoded in the first data signal is latched to obtain a first bit pattern. A second bit pattern is obtained, and, based on a comparison of the first bit pattern to the second bit pattern, the I/O receivers of the memory die are activated.Type: ApplicationFiled: June 3, 2022Publication date: December 7, 2023Inventors: SNEHA BHATIA, Sajal Mittal, Venkatesh Prasad Ramachandra, Anil Pai
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Publication number: 20230386600Abstract: Systems and methods are provided that combine a write duty cycle adjuster with write training to reduce detection and duty cycle errors in memory devices. Various embodiments herein perform write duty cycle adjuster operations to adjust a duty cycle of a clock signal that coordinates a data signal with a data operation on the memory device based on an error in the duty cycle, and performs write training operations to detect a skew between the data signal and the clock signal and adjust a sampling transition of the duty cycle of the clock signal to align with a valid data window of the data signal.Type: ApplicationFiled: May 31, 2022Publication date: November 30, 2023Inventors: Jang Woo Lee, Srinivas Rajendra, Anil Pai, Venkatesh Prasad Ramachandra
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Publication number: 20230386531Abstract: A command/address sequence associated with a read/write operation for a memory device utilizes various existing command/address clock signals in a novel way that obviates the need to utilize the I/O bus. As such, the command/address sequence can be performed in parallel with the DIN/DOUT operations, thereby removing the performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence encodes bit information on first and second enable signals and utilizes rising or falling edges of a clock signal to latch the encoded bit information, which can then be decoded to determine corresponding command and address codes. A chip select sequence is also disclosed that enables a memory chip configuration to be employed in which each chip in a package shares a common connection to a controller but does not require hard-coded pins for performing chip select.Type: ApplicationFiled: May 31, 2022Publication date: November 30, 2023Inventors: TIANYU TANG, Siddhesh Darne, Venkatesh Prasad Ramachandra
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Publication number: 20230386584Abstract: Systems and methods are provided for correcting errors in unmatched memory devices. Various embodiments herein train a memory interface to determine a duty cycle timing for a clock signal in a data window formed by a data signal in a memory cell. The duty cycle timing identifies an initial trained timing in the data window at which a setup portion and a hold portion of the data window are approximately equal in length when the trigger signal is received at the initial trained timing. The embodiments herein also identify an event that shifts the duty cycle timing away from the initial trained timing, and triggers a retraining of the memory interface based on a determination that at least one of two points defined about the initial trained timing fails a two-point sampling.Type: ApplicationFiled: May 27, 2022Publication date: November 30, 2023Inventors: Venkatesh Prasad RAMACHANDRA, Jang Woo LEE, Srinivas RAJENDRA, Anil PAI
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Publication number: 20230377677Abstract: Techniques for mitigating/eliminating the impact of duty distortion caused by delays in clock paths within a built-in high-frequency test circuit for NAND flash are disclosed. By mitigating or eliminating the impact of duty distortion, accuracy of the valid data window measurement is ensured. Rising edges of a strobe clock signal and an inverted strobe clock signal are used to respectively locate even and odd data (or vice versa) within an input buffer of the NAND flash during respective sweeps of the strobe and inverted strobe clock signals. In this manner, even if the strobe clock signal's duty ratio is distorted, there is no impact on the valid data window measurement. Further, read latency is used to introduce delay to a read enable (RE) clock signal, thereby obviating the need for a replica controlled delay in the RE clock path and eliminating the duty distortion that would otherwise occur.Type: ApplicationFiled: May 20, 2022Publication date: November 23, 2023Inventors: HOON CHOI, Anil Pai, Venkatesh Prasad Ramachandra
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Patent number: 11303276Abstract: An active termination circuit comprising an input node connected to a transmission line, a first transistor, and a second transistor. The transmission line supplies a signal to the input node. The first transistor is diode connected between a high voltage supply and the input node. The first transistor terminates the signal when the signal is at a low logic level. The second transistor is diode connected between the input node and a low voltage supply. The second transistor terminates the signal when the signal is at a high logic level.Type: GrantFiled: February 26, 2021Date of Patent: April 12, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: John Thomas Contreras, Rehan Ahmed Zakai, Srinivas Rajendra, Venkatesh Prasad Ramachandra
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Publication number: 20220052688Abstract: An active termination circuit comprising an input node connected to a transmission line, a first transistor, and a second transistor. The transmission line supplies a signal to the input node. The first transistor is diode connected between a high voltage supply and the input node. The first transistor terminates the signal when the signal is at a low logic level. The second transistor is diode connected between the input node and a low voltage supply. The second transistor terminates the signal when the signal is at a high logic level.Type: ApplicationFiled: February 26, 2021Publication date: February 17, 2022Inventors: John Thomas CONTRERAS, Rehan Ahmed ZAKAI, Srinivas RAJENDRA, Venkatesh Prasad RAMACHANDRA
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Patent number: 11184007Abstract: Circuits and systems for generating counter signals are provided herein. A circuit may comprise a shift register having a series of flip-flops. Each of the flip-flops of the series may be coupled to a clock. The shift register may generate a borrowing clock signal using an output of a flip-flop of the shift register, and a transition of the borrowing clock signal may be advanced by a number of clock cycles based on a position of the flip-flop of the shift register. The circuit may further comprise a clock divider circuit having a number of divide-by-N counters and a number of flip-flops. A divide-by-N counter may be coupled to a flip-flop of the shift register, and a flip-flop of the clock divider circuit may be coupled to one of the divide-by-N counters and to the clock.Type: GrantFiled: March 10, 2020Date of Patent: November 23, 2021Assignee: Western Digital Technologies, Inc.Inventors: Tianyu Tang, Venkatesh prasad Ramachandra
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Publication number: 20210288652Abstract: Circuits and systems for generating counter signals are provided herein. A circuit may comprise a shift register having a series of flip-flops. Each of the flip-flops of the series may be coupled to a clock. The shift register may generate a borrowing clock signal using an output of a flip-flop of the shift register, and a transition of the borrowing clock signal may be advanced by a number of clock cycles based on a position of the flip-flop of the shift register. The circuit may further comprise a clock divider circuit having a number of divide-by-N counters and a number of flip-flops. A divide-by-N counter may be coupled to a flip-flop of the shift register, and a flip-flop of the clock divider circuit may be coupled to one of the divide-by-N counters and to the clock.Type: ApplicationFiled: March 10, 2020Publication date: September 16, 2021Applicant: Western Digital Technologies, Inc.Inventors: Tianyu Tang, Venkatesh Prasad Ramachandra
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Publication number: 20160204783Abstract: A circuit is presented to reduce power while transmitting high speed signals across a long length of wire on an integrated circuit. A PMOS is used as a low swing driver, where the PMOS is connected between the driver's output and ground. The gate of the PMOS is also set to ground, while the input signal is connected to the bulk. The output is then transmitted over the signal path to an analogue receiver, where both single ended and differential embodiments are presented. For a single ended version, a reference voltage for the receiver can be provided by a second, similarly connected PMOS whose bulk has an input signal at an intermediate level of input swing at the transmitter PMOS.Type: ApplicationFiled: January 14, 2015Publication date: July 14, 2016Inventors: Srinivas Rajendra, Venkatesh Prasad Ramachandra
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Patent number: 9385721Abstract: A circuit is presented to reduce power while transmitting high speed signals across a long length of wire on an integrated circuit. A PMOS is used as a low swing driver, where the PMOS is connected between the driver's output and ground. The gate of the PMOS is also set to ground, while the input signal is connected to the bulk. The output is then transmitted over the signal path to an analog receiver, where both single ended and differential embodiments are presented. For a single ended version, a reference voltage for the receiver can be provided by a second, similarly connected PMOS whose bulk has an input signal at an intermediate level of input swing at the transmitter PMOS.Type: GrantFiled: January 14, 2015Date of Patent: July 5, 2016Assignee: SanDisk Technologies LLCInventors: Srinivas Rajendra, Venkatesh Prasad Ramachandra
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Patent number: 8923065Abstract: Each I/O channel between a controller and one or more memory dice of a memory device has a driver on one end and a receiver at the other end. The receiver is optionally terminated with a pseudo open-drain (“POD”) termination instead of the conventional center-tapped (“CTT”) termination to save energy. During a read operation, data is driven from the memory die to a POD terminated receiver circuit in the controller. With POD termination, the degradation in performance due to the more non-linear driver in the memory die, fabricated for example in the NAND technology processing, is alleviated by an adaptive reference voltage level adjustment in the receiver circuit of the controller. Optionally, the receiver circuit of a memory die is also provided with an adaptive reference level adjustment.Type: GrantFiled: March 13, 2013Date of Patent: December 30, 2014Assignee: SanDisk Technologies, Inc.Inventor: Venkatesh Prasad Ramachandra
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Publication number: 20140185374Abstract: Each I/O channel between a controller and one or more memory dice of a memory device has a driver on one end and a receiver at the other end. The receiver is optionally terminated with a pseudo open-drain (“POD”) termination instead of the conventional center-tapped (“CTT”) termination to save energy. During a read operation, data is driven from the memory die to a POD terminated receiver circuit in the controller. With POD termination, the degradation in performance due to the more non-linear driver in the memory die, fabricated for example in the NAND technology processing, is alleviated by an adaptive reference voltage level adjustment in the receiver circuit of the controller. Optionally, the receiver circuit of a memory die is also provided with an adaptive reference level adjustment.Type: ApplicationFiled: March 13, 2013Publication date: July 3, 2014Applicant: SanDisk Technologies Inc.Inventor: Venkatesh Prasad Ramachandra