Patents by Inventor Venkatraghavan Bringivijayaraghavan
Venkatraghavan Bringivijayaraghavan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9607668Abstract: Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage representative of data to be placed on the first line and then precharged to a first precharge voltage. A second line is configured to be driven to a second voltage representative of data to be placed on the second line and then precharged to a second precharge voltage. A charge sharing device is coupled between the first line and the second line. The charge sharing device is configured to selectively allow charge from the first line to flow to the second line after the first and second lines are driven to the respective first and second voltages representative of data to be placed on the respective lines.Type: GrantFiled: August 29, 2014Date of Patent: March 28, 2017Assignee: Micron Technology, Inc.Inventor: Venkatraghavan Bringivijayaraghavan
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Publication number: 20170053694Abstract: Approaches for providing write-assist for a Static Random Access Memory (SRAM) array are provided. A circuit includes a control circuit connected to a cell in a SRAM array. The control circuit is configured to: apply a first voltage to a first pull down transistor of the cell during a write operation to the cell; and apply a second voltage, different than the first voltage, to a second pull down transistor of the cell during the write operation.Type: ApplicationFiled: August 21, 2015Publication date: February 23, 2017Inventors: George M. Braceras, Venkatraghavan Bringivijayaraghavan, Sheikh S. Chishti
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Patent number: 9570156Abstract: Approaches for providing write-assist for a Static Random Access Memory (SRAM) array are provided. A circuit includes a control circuit connected to a cell in a SRAM array. The control circuit is configured to: apply a first voltage to a first pull down transistor of the cell during a write operation to the cell; and apply a second voltage, different than the first voltage, to a second pull down transistor of the cell during the write operation.Type: GrantFiled: August 21, 2015Date of Patent: February 14, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: George M. Braceras, Venkatraghavan Bringivijayaraghavan, Sheikh S. Chishti
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Patent number: 9570155Abstract: Approaches for stability of cells in a Static Random Access Memory (SRAM) array are provided. A circuit includes a precharging circuit configured to precharge bitlines of a Static Random Access Memory (SRAM) array to a first voltage potential for a non-read operation and to a second voltage potential for a read operation. The first voltage potential is different than the second voltage potential.Type: GrantFiled: June 9, 2015Date of Patent: February 14, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: George M. Braceras, Venkatraghavan Bringivijayaraghavan, Krishnan S. Rengarajan, Arjun Sankar, Sreenivasula R. Dhani Reddy
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Patent number: 9548104Abstract: Approaches for providing write-assist boost for a Static Random Access Memory (SRAM) array are provided. A circuit includes a write driver of a Static Random Access Memory (SRAM) array. The circuit also includes a boost circuit that dynamically varies a write-assist boost voltage based on a stability assist setting applied to a wordline of the array.Type: GrantFiled: June 30, 2015Date of Patent: January 17, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: George M. Braceras, Venkatraghavan Bringivijayaraghavan, Krishnan S. Rengarajan, Rahul Nayak
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Publication number: 20170004874Abstract: Approaches for providing write-assist boost for a Static Random Access Memory (SRAM) array are provided. A circuit includes a write driver of a Static Random Access Memory (SRAM) array. The circuit also includes a boost circuit that dynamically varies a write-assist boost voltage based on a stability assist setting applied to a wordline of the array.Type: ApplicationFiled: June 30, 2015Publication date: January 5, 2017Inventors: George M. Braceras, Venkatraghavan Bringivijayaraghavan, Krishnan S. Rengarajan, Rahul Nayak
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Publication number: 20160365139Abstract: Approaches for stability of cells in a Static Random Access Memory (SRAM) array are provided. A circuit includes a precharging circuit configured to precharge bitlines of a Static Random Access Memory (SRAM) array to a first voltage potential for a non-read operation and to a second voltage potential for a read operation. The first voltage potential is different than the second voltage potential.Type: ApplicationFiled: June 9, 2015Publication date: December 15, 2016Inventors: George M. Braceras, Venkatraghavan Bringivijayaraghavan, Krishnan S. Rengarajan, Arjun Sankar, Sreenivasula R. Dhani Reddy
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Patent number: 9437282Abstract: A sense amplifier device for sensing a differential signal produced by a memory cell includes a first n-type metal-oxide-semiconductor field-effect transistor (NMOS) stack having multiple NMOS devices sharing a gate connection connected to a complementary data line; and a second NMOS stack having multiple NMOS devices sharing a gate connection connected to a true data line. At least one of the devices in the first stack has higher gate-to-source and drain-to-source voltages than a gate-to-source and drain-to-source voltages of at least one device in the second stack when the voltage of the complementary data line is higher than the true data line. At least one of the devices in the second stack has a higher gate-to-source and drain-to-source voltages than the gate-to-source and drain-to-source voltages of at least one device in the first stack when the voltage of the true data line is higher than the complementary data line.Type: GrantFiled: August 6, 2015Date of Patent: September 6, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: George M. Braceras, Venkatraghavan Bringivijayaraghavan, Krishnan S. Rengarajan
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Patent number: 9405468Abstract: A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects. The stack may include a plurality of memory chips, a primary control chip, and a secondary control chip. The primary and secondary control chips may be electrically connected to the plurality of memory chips by an internal data bus. The primary control chip may have logic to provide an interface between the internal data bus and a first external data bus. The secondary control chip may have logic to provide an interface between the internal data bus and a second external data bus.Type: GrantFiled: May 13, 2014Date of Patent: August 2, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Venkatraghavan Bringivijayaraghavan, Saurabh Chadha, Abhijit Saurabh, Saravanan Sethuraman, Kenneth L. Wright
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Patent number: 9400602Abstract: A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects. The stack may include a plurality of memory chips, a primary control chip, and a secondary control chip. The primary and secondary control chips may be electrically connected to the plurality of memory chips by an internal data bus. The primary control chip may have logic to provide an interface between the internal data bus and a first external data bus. The secondary control chip may have logic to provide an interface between the internal data bus and a second external data bus.Type: GrantFiled: August 20, 2014Date of Patent: July 26, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Venkatraghavan Bringivijayaraghavan, Saurabh Chadha, Abhijit Saurabh, Saravanan Sethuraman, Kenneth L. Wright
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Patent number: 9390769Abstract: Multiplexed latches include a multiplexor having a first data input, a second data input, a selection input, and a multiplexor output. A first latch has a first latch clock input, and a first latch output. A second latch has a second latch clock input, and a second latch output. The first latch output is connected to the first data input of the multiplexor, and the second latch output is connected to the second data input of the multiplexor. A feedback loop connects the multiplexor output to the first latch clock input and the second latch clock input. When the selection signal is received by the multiplexor, the feedback loop feeds the output from the multiplexor back to the latches to maintain the existing latch output until the clock signal transitions, to avoid glitches in the multiplexor output when the selection signal and clock signal are not synchronized.Type: GrantFiled: October 26, 2015Date of Patent: July 12, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Vinay Bhatsoori, George M. Braceras, Venkatraghavan Bringivijayaraghavan
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Publication number: 20160164497Abstract: A circuit structure is provided. The circuit structure includes first pfet device. The circuit structure further includes a first nfet device connected to the pfet device. The circuit structure further includes a keeper nfet device that reduces stress associated with the first nfet device by keeping the first nfet device off during its functional state. The circuit structure further includes a keeper pfet device that reduces stress associated with the first pfet device by keeping the first pfet device off during its functional state.Type: ApplicationFiled: December 4, 2014Publication date: June 9, 2016Inventors: Navin Agarwal, Igor Arsovski, Venkatraghavan Bringivijayaraghavan, Krishnan S. Rengarajan
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Patent number: 9281045Abstract: A first data access request to a first row of a first memory array of the DRAM is received while a refresh operation in the first memory array is executing. The refresh operation is paused. The first data access request is executed, and simultaneously, the bits of the first row of the first memory array, including any updates indicated in the first data access request, are latched to a transfer register. The bits latched to the transfer register are written to a corresponding first row in a second memory array of the DRAM. A bank select logic is updated to indicate that subsequent data access requests to the first row in the first memory array will be executed from the second memory array. The refresh operation is then resumed.Type: GrantFiled: December 16, 2014Date of Patent: March 8, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Darren L. Anand, Venkatraghavan Bringivijayaraghavan, Krishnan S. Rengarajan
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Patent number: 9251890Abstract: A memory device with an age-detect-and-correct (ADAC) circuit that detects skew caused by bias temperature instability fatigue (that is, bias temperature instability stress accumulated over time), and counters skew by selectively adjusting the proportion (measured temporally) of active state operation to idle state operation. Also, a memory burn-in device using a similar ADAC circuit.Type: GrantFiled: December 19, 2014Date of Patent: February 2, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Navin Agarwal, Igor Arsovski, Venkatraghavan Bringivijayaraghavan, Krishnan S. Rengarajan
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Publication number: 20160027706Abstract: Various embodiments comprise apparatuses and methods for testing and repairing through-substrate vias in a stack of interconnected dice. In various embodiments, an apparatus is provided that includes a number of through-substrate vias to couple to one or more devices, at least one redundant through-substrate via to allow a repair of the apparatus, and a pair of pull-up devices coupled to the through-substrate vias and the redundant through-substrate via to provide a high-data value to the first end of the respective through-substrate vias. A test register is coupled the second end of each of the through-substrate vias and the redundant through-substrate via to store a received version of the high-data value. A comparator compares the high-data value with the received version of the high-data value to test the through-substrate vias for short-circuit connections.Type: ApplicationFiled: October 7, 2015Publication date: January 28, 2016Inventors: Venkatraghavan Bringivijayaraghavan, Jason M. Brown
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Patent number: 9236116Abstract: Memory cells with read assist schemes and methods of use are provided. The memory includes a plurality of rows and columns, each of which include a memory cell having a pull-down device. The memory further includes at least one boost circuit connected to each of the memory cells and which provides a negative boost signal to the pull-down devices during read access.Type: GrantFiled: March 26, 2015Date of Patent: January 12, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: George M. Braceras, Venkatraghavan Bringivijayaraghavan, Binu Jose, Krishnan S. Rengarajan
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Patent number: 9208859Abstract: A memory circuit configured for reducing dynamic read power is disclosed that includes a first read global bit line connected to a first sense amp and a second read global bit line connected to a second sense amp. The second read global bit line is adjacent to the first read global bit line. The memory circuit further includes a third read global bit line and logic circuitry connected to the first read global bit line, the second read global bit line, and the third read global bit line. The logic circuitry is configured to determine when both the first read global bit line and the second read global bit line are evaluated as in a high state, and in response to the determining, toggle the third read global bit line to the high state.Type: GrantFiled: August 22, 2014Date of Patent: December 8, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Venkatraghavan Bringivijayaraghavan, Dhani Reddy Sreenivasula Reddy
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Publication number: 20150331767Abstract: A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects. The stack may include a plurality of memory chips, a primary control chip, and a secondary control chip. The primary and secondary control chips may be electrically connected to the plurality of memory chips by an internal data bus. The primary control chip may have logic to provide an interface between the internal data bus and a first external data bus. The secondary control chip may have logic to provide an interface between the internal data bus and a second external data bus.Type: ApplicationFiled: August 20, 2014Publication date: November 19, 2015Inventors: Venkatraghavan Bringivijayaraghavan, Saurabh Chadha, Abhijit Saurabh, Saravanan Sethuraman, Kenneth L. Wright
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Publication number: 20150332736Abstract: A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects. The stack may include a plurality of memory chips, a primary control chip, and a secondary control chip. The primary and secondary control chips may be electrically connected to the plurality of memory chips by an internal data bus. The primary control chip may have logic to provide an interface between the internal data bus and a first external data bus. The secondary control chip may have logic to provide an interface between the internal data bus and a second external data bus.Type: ApplicationFiled: May 13, 2014Publication date: November 19, 2015Applicant: International Business Machines CorporationInventors: Venkatraghavan Bringivijayaraghavan, Saurabh Chadha, Abhijit Saurabh, Saravanan Sethuraman, Kenneth L. Wright
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Patent number: 9157960Abstract: Various embodiments comprise apparatuses and methods for testing and repairing through-substrate vias in a stack of interconnected dice. In various embodiments, an apparatus is provided that includes a number of through-substrate vias to couple to one or more devices, at least one redundant through-substrate via to allow a repair of the apparatus, and a pair of pull-up devices coupled to the through-substrate vias and the redundant through-substrate via to provide a high-data value to the first end of the respective through-substrate vias. A test register is coupled the second end of each of the through-substrate vias and the redundant through-substrate via to store a received version of the high-data value. A comparator compares the high-data value with the received version of the high-data value to test the through-substrate vias for short-circuit connections.Type: GrantFiled: March 2, 2012Date of Patent: October 13, 2015Assignee: Micron Technology, Inc.Inventors: Venkatraghavan Bringivijayaraghavan, Jason M. Brown