Patents by Inventor Venkatraman Iyer

Venkatraman Iyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Link power savings with state retention
    Patent number: 10175744
    Abstract: Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a serial link are turned off during idle periods while retaining link state in each agent. Other embodiments are also disclosed.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Naveen Cherukuri, Jeffrey Wilcox, Venkatraman Iyer, Selim Bilgin, David S. Dunning, Robin Tim Frodsham, Theodore Z. Schoenborn, Sanjay Dabral
  • Pharmaceutical formulations comprising substituted pyrazolo[5,1-c]pyrido[4,3-e][1,2,4]triazines for treating lysosomal storage disorders
    Patent number: 10166236
    Abstract: This disclosure provides compounds, such as compounds of Formula I: pharmaceutical formulations thereof, and related methods of use for the treatment of defects of cholesterol homeostasis including lysosomal storage disorders such as Niemann-Pick Type C disease.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: January 1, 2019
    Assignee: Perlara PBC
    Inventors: Ethan Oren Perlstein, Nina Di Primio, Tom Aaron Hartl, Sangeetha Venkatraman Iyer, Alexander James Ludin, Tamy May Sharly Portillo Rodriguez, John Alan Tucker
  • Link-physical layer interface adapter
    Patent number: 10152446
    Abstract: An interface adapter to identify a first ready signal from a first link layer-to-physical layer (LL-PHY) interface of a first communication protocol indicating readiness of a physical layer of the first protocol to accept link layer data. The interface adapter generates a second ready signal compatible with a second LL-PHY interface of a second communication protocol to cause link layer data to be sent from a link layer of the second communication protocol according to a predefined delay. A third ready signal is generated compatible with the first LL-PHY interface to indicate to the physical layer of the first communication protocol that the link layer data is to be sent. The interface adapter uses a shift register to cause the link layer data to be passed to the physical layer according to the predefined delay.
    Type: Grant
    Filed: October 1, 2016
    Date of Patent: December 11, 2018
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Mahesh Wagh, William R. Halleck, Rahul R. Shah
  • High performance interconnect physical layer
    Patent number: 10146733
    Abstract: A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: December 4, 2018
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Debendra Das Sharma, Jeffrey C. Swanson
  • EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE
    Publication number: 20180276164
    Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.
    Type: Application
    Filed: September 25, 2015
    Publication date: September 27, 2018
    Inventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
  • High performance repeater
    Patent number: 10050623
    Abstract: A redriver device is provided to receive signals from a first device and forward the signals to a second device on a differential link. Detection circuitry is provided to detect presence of the second device on the link by detecting a pulldown voltage generated from termination of the second device on the link, and pulldown relay circuitry is provided to generate an emulated version of the pulldown voltage of the second device on pins to connect to the first device in response to detecting presence of the second device on the link.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: August 14, 2018
    Assignee: Intel Corporation
    Inventors: Kai Xiao, Zuoguo Wu, Venkatraman Iyer
  • HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER
    Publication number: 20180203811
    Abstract: Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a pre-defined sequence on cach of the lanes.
    Type: Application
    Filed: March 12, 2018
    Publication date: July 19, 2018
    Inventors: Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Ashish Gupta
  • High performance interconnect
    Patent number: 10025746
    Abstract: A signal is received, a boundary of which is to be sent in alignment with a sync counter value. A nominal latency of a link is determined based on the sync counter value. Additional latency is applied to the signal to increase the nominal latency to a target latency for the link.
    Type: Grant
    Filed: December 20, 2014
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventors: William R. Halleck, Rahul Shah, Venkatraman Iyer
  • Multichip Package Link Error Detection
    Publication number: 20180196710
    Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.
    Type: Application
    Filed: September 26, 2015
    Publication date: July 12, 2018
    Applicant: INTEL CORPORATION
    Inventors: Venkatraman Iyer, Robert G. Blankenship, Mahesh Wagh, Zuoguo Wu
  • HIGH SPEED INTERCONNECT WITH CHANNEL EXTENSION
    Publication number: 20180191523
    Abstract: An apparatus includes an agent to facilitate communication in one of two or more modes, where a first of the two or more modes involves communication over links including a first number of lanes and a second of the two or more modes involves communication over links including a second number of lanes, and the first number is greater than the second number. The apparatus further includes a memory including data to indicate which of the two or modes applies to a particular link and a multiplexer to reverse lane numbering on links including either the first number of lanes or the second number of lanes.
    Type: Application
    Filed: December 29, 2016
    Publication date: July 5, 2018
    Inventors: Rahul R. Shah, William R. Halleck, Fulvio Spagna, Venkatraman Iyer
  • HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER
    Publication number: 20180189201
    Abstract: A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS) followed by a number of consecutive training sequences. Instances of the EIEOS are to be aligned with a rollover of a sync counter. A latency value is determined from one of the EIEOS instances in the supersequence and latency is added to a receive path of the link through a latency buffer based on the latency value.
    Type: Application
    Filed: December 21, 2017
    Publication date: July 5, 2018
    Applicant: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Jeff Willey, Robert G. Blankenship
  • BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS
    Publication number: 20180181525
    Abstract: Systems, methods, and apparatuses involve a PHY coupled to a MAC. The PHY can include a drift buffer coupled to an output of a receiver and a bypass branch coupled to the output of the receiver. The PHY includes a clocking multiplexer that includes a first clock input coupled to a recovered clock of the PHY and a second clock input coupled to a p-clock of the MAC; and a clock output configured to output one of the recovered clock or the p-clock based on a selection input value. The PHY includes a bypass multiplexer that includes a first data input coupled to an output of a drift buffer and a second data input coupled to the bypass branch; and a data output configured to output one of the output of the drift buffer or data from the bypass branch based on the section input value of the clocking multiplexer.
    Type: Application
    Filed: December 26, 2016
    Publication date: June 28, 2018
    Inventors: Venkatraman Iyer, William R. Halleck, Rahul R. Shah, Eric Lee
  • LOW LATENCY RETIMER
    Publication number: 20180181502
    Abstract: A retimer device receives a first signal from a first device and regenerates the first signal to send to a second device. The retimer further receive a second signal from the second device and regenerates the second signal to send to the first device, where the first device includes a processor device. The retimer includes a sideband interface to connect to the first device and further includes protocol logic to monitor the first signal, determine that the first signal includes a pattern defined in a protocol to identify a protocol activity, and participate in performance of the protocol activity using the sideband interface.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 28, 2018
    Inventors: Michelle Jen, Debendra Das Sharma, Venkatraman Iyer, Tao Liang
  • High performance interconnect physical layer
    Patent number: 10002095
    Abstract: A set of training sequences is generated, each training sequence to include a respective training sequence header, and the training sequence header is to be DC-balanced over the set of training sequences. The set of training sequences can be combined with electric ordered sets to form supersequences for use in such tasks as link adaptation, link state transitions, byte lock, deskew, and other tasks.
    Type: Grant
    Filed: March 28, 2015
    Date of Patent: June 19, 2018
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Sitaraman V. Iyer
  • Automated detection of high performance interconnect coupling
    Patent number: 9965370
    Abstract: A port of a first device includes remote device detection logic to detect, on a link, a remote second device, determine, from a voltage generated at the port, whether the second device is direct current (DC)-coupled or alternating current (AC)-coupled to the link, and select one of first settings or second settings to be applied at the port in communications over the link with the second device based on whether the second device is DC-coupled or AC-coupled.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: May 8, 2018
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Zuoguo Wu, Jeffrey Ou, Sitaraman Iyer
  • Multichip package link
    Patent number: 9946676
    Abstract: A system-on-a-chip, such as a logical PHY, may be divided into hard IP blocks with fixed routing, and soft IP blocks with flexible routing. Each hard IP block may provide a fixed number of lanes. Using p hard IP blocks, where each block provides n data lanes, h=n*p total hard IP data lanes are provided. Where the system design calls for k total data lanes, it is possible that k?h, so that ?k/n? hard IP blocks provide h=n*p available hard IP data lanes. In that case, h?k lanes may be disabled. In cases where lane reversals occur, such as between hard IP and soft IP, bowtie routing may be avoided by the use of a multiplexer-like programmable switch within the soft IP.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: April 17, 2018
    Assignee: Intel Corporation
    Inventors: Mahesh Wagh, Zuoguo Wu, Venkatraman Iyer, Gerald S. Pasdast, Mark S. Birrittella, Ishwar Agarwal, Lip Khoon Teh, Su Wei Lim, Anoop Kumar Upadhyay
  • HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER
    Publication number: 20180095927
    Abstract: A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.
    Type: Application
    Filed: November 22, 2017
    Publication date: April 5, 2018
    Applicant: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Rahul C. Shah, Arvind A. Kumar
  • VOLTAGE MODULATED CONTROL LANE
    Publication number: 20180095925
    Abstract: A computing component is provided with physical layer logic to receive data on a physical link including a plurality of lanes, where the data is received from a particular component on one or more data lanes of the physical link. The physical layer is further to receive a stream signal on a particular one of the plurality of lanes of the physical link, where the stream signal is to identify a type of the data on the one or more data lanes, the type is one of a plurality of different types supported by the particular component, and the stream signal is encoded through voltage amplitude modulation on the particular lane.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: Venkatraman Iyer, Zuoguo Wu, Mahesh Wagh
  • LINK-PHYSICAL LAYER INTERFACE ADAPTER
    Publication number: 20180095923
    Abstract: An interface adapter to identify a first ready signal from a first link layer-to-physical layer (LL-PHY) interface of a first communication protocol indicating readiness of a physical layer of the first protocol to accept link layer data. The interface adapter generates a second ready signal compatible with a second LL-PHY interface of a second communication protocol to cause link layer data to be sent from a link layer of the second communication protocol according to a predefined delay. A third ready signal is generated compatible with the first LL-PHY interface to indicate to the physical layer of the first communication protocol that the link layer data is to be sent. The interface adapter uses a shift register to cause the link layer data to be passed to the physical layer according to the predefined delay.
    Type: Application
    Filed: October 1, 2016
    Publication date: April 5, 2018
    Applicant: Intel Corporation
    Inventors: Venkatraman Iyer, Mahesh Wagh, William R. Halleck, Rahul R. Shah
  • Low power entry in a shared memory link
    Patent number: 9921768
    Abstract: Data is sent to correspond to a load/store-type operation associated with shared memory over a link according to a memory access link protocol and the memory access link protocol is to be overlaid on another, different link protocol. A request is sent to enter a low power state, where the request is to include a data value encoded in a field of a token, the token is to indicate a start of packet data and is to further indicate whether subsequent data to be sent after the token is to include data according to one of the other link protocol and the memory access link protocol.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: March 20, 2018
    Assignee: Intel Corporation
    Inventors: Michelle C. Jen, Debendra Das Sharma, Mahesh Wagh, Venkatraman Iyer