Patents by Inventor Venugopal Balasubramonian
Venugopal Balasubramonian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220247652Abstract: An integrated Circuit (IC) for use in a network device includes a receiver and a Link Quality Estimation Circuit (LQEC). The receiver is configured to receive a signal over a link and to process the received signal. The LQEC is configured to predict a link quality measure indicative of communication quality over the link in the future, by analyzing at least one or more settings of circuitry of the receiver, and to initiate a responsive action depending on the predicted link quality measure.Type: ApplicationFiled: January 27, 2022Publication date: August 4, 2022Inventors: Venugopal Balasubramonian, Lenin Kumar Patra
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Patent number: 10256944Abstract: A device includes a network interface that includes a physical coding sublayer (PCS) unit. The PCS unit receives an Ethernet packet. The PCS unit encode the Ethernet packet into a transmission frame that includes a first set of bit fields corresponding to contents of the Ethernet packet and a second set of bit fields corresponding to control information for the encoding. The PCS unit computes a validity value of the transmission frame, wherein the validity value is based on the first set of bit fields included in the transmission frame. The PCS unit inserts the validity value of the transmission frame into one or more idle bit fields in the second set of bit fields included in the transmission frame. The PCS unit processes the transmission frame for sending to a receiving device over a physical medium.Type: GrantFiled: April 19, 2016Date of Patent: April 9, 2019Assignee: Marvell International Ltd.Inventors: Junqing Sun, Venugopal Balasubramonian
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Patent number: 8938250Abstract: A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.Type: GrantFiled: July 25, 2013Date of Patent: January 20, 2015Assignee: Intel Mobible Communications GmbHInventors: Song Chen, Paul L. Chou, Christopher C. Woodthorpe, Venugopal Balasubramonian, Keith Rieken
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Publication number: 20130346726Abstract: A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.Type: ApplicationFiled: July 25, 2013Publication date: December 26, 2013Applicant: Intel Mobile Communications GmbHInventors: Song CHEN, Paul L. Chou, Christopher C. Woodthorpe, Venugopal Balasubramonian, Keith Rieken
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Patent number: 8526965Abstract: A wireless communication base station comprising a plurality of application specific instruction set processors (ASISPs) configured to support one or more processes hosted by the base station, and to track process state information associated with each of the processes; and a memory configured to store the tracked process state information, and when an ASISP of the plurality of ASISPs is reallocated from a first process to a second process, the respective ASISP is configured to retrieve from the memory process state information for the second process.Type: GrantFiled: June 22, 2012Date of Patent: September 3, 2013Assignee: Intel Mobile Communications GmbHInventors: Song Chen, Paul L. Chou, Christopher C. Woodthorpe, Venugopal Balasubramonian, Keith Rieken
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Publication number: 20120272042Abstract: A wireless communication base station comprising a plurality of application specific instruction set processors (ASISPs) configured to support one or more processes hosted by the base station, and to track process state information associated with each of the processes; and a memory configured to store the tracked process state information, and when an ASISP of the plurality of ASISPs is reallocated from a first process to a second process, the respective ASISP is configured to retrieve from the memory process state information for the second process.Type: ApplicationFiled: June 22, 2012Publication date: October 25, 2012Inventors: Song CHEN, Paul L. Chou, Christopher C. Woodthorpe, Venugopal Balasubramonian, Keith Rieken
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Patent number: 8244270Abstract: A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.Type: GrantFiled: July 29, 2011Date of Patent: August 14, 2012Assignee: Intel Mobile Communications GmbHInventors: Song Chen, Paul L. Chou, Christopher C. Woodthorpe, Venugopal Balasubramonian, Keith Rieken
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Publication number: 20110314257Abstract: A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.Type: ApplicationFiled: July 29, 2011Publication date: December 22, 2011Inventors: Song CHEN, Paul L. CHOU, Christopher C. WOODTHORPE, Venugopal BALASUBRAMONIAN, Keith RIEKEN
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Patent number: 8014786Abstract: A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.Type: GrantFiled: August 20, 2007Date of Patent: September 6, 2011Assignee: Infineon Technologies AGInventors: Song Chen, Paul L. Chou, Christopher C. Woodthorpe, Venugopal Balasubramonian, Keith Rieken
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Patent number: 7627031Abstract: An apparatus and method for adaptively introducing a compensating signal latency related to a signal latency of a data symbol decision circuit. Adaptive timing control circuitry, including an interpolating mixer implemented as a tapped delay line with correlated tap coefficients, introduces a latency adaptively and substantially matching the latency of the data decision circuit for use within an adaptive equalizer, thereby minimizing the mean-squared error of such decision circuit. This adaptive latency is used in generating the feedback error signal which, in turn, can be used by the feedforward equalizer for dynamically adjusting its adaptive filter tap coefficients.Type: GrantFiled: July 21, 2005Date of Patent: December 1, 2009Assignee: Scintera Networks Inc.Inventors: Qian Yu, Venugopal Balasubramonian, Jishnu Bhattacharjee, Debanjan Mukherjee, Abhijit Phanse, Abhijit G. Shanbhag, Edem Ibragimov, Fabian Giroud
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Patent number: 7606576Abstract: A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.Type: GrantFiled: July 24, 2001Date of Patent: October 20, 2009Assignee: Infineon Technologies AGInventors: Song Chen, Paul L. Chou, Christopher C. Woodthorpe, Venugopal Balasubramonian, Keith Rieken
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Patent number: 7561617Abstract: Systems and methods are disclosed to provide channel monitoring and/or performance monitoring for a communication channel. For example, in accordance with an embodiment of the present invention, an equalizer is disclosed that equalizes for channel distortions and also provides channel and performance monitoring information, such as for example bandwidth estimation, channel identification, signal-to-noise ratio, chromatic dispersion, and/or polarization-mode dispersion.Type: GrantFiled: September 21, 2007Date of Patent: July 14, 2009Assignee: INPHI CorporationInventors: Abhijit G. Shanbhag, Abhijit Phanse, Jishnu Bhattacharjee, Debanjan Mukherjee, Prashant Choudhary, Edem Ibragimov, Venugopal Balasubramonian, Qian Yu, Madabusi Govindarajan
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Patent number: 7421021Abstract: An adaptive signal equalizer with a feedforward filter in which the feedback error signal and corresponding incoming data signal are dynamically aligned in time using signal interpolation, and further, to control the precursor/postcursor filter taps configuration, thereby producing more adaptive filter tap coefficient signals for significantly improved and robust signal equalization.Type: GrantFiled: June 7, 2007Date of Patent: September 2, 2008Assignee: Inphi CorporationInventors: Venugopal Balasubramonian, Jishnu Bhattacharjee, Edem Ibragimov, Debanjan Mukherjee, Abhijit Phanse, Abhijit Shanbhag, Qian Yu
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Patent number: 7421022Abstract: A continuous time electronic dispersion compensation architecture using feed forward equalization and a non-linear decision feedback equalization forms an output signal by a linear combination of successively delayed versions of the input signal and the sliced output signal weighted by appropriate coefficients. A selected number of taps in the mixer used to generate a corresponding number of coefficients for use in the feed forward equalizer are held to a selected voltage to ensure that the coefficients associated with these two taps do not drift. This causes the other coefficients to converge to a unique minimum square error value. In one embodiment the selected voltage is the maximum system voltage.Type: GrantFiled: April 27, 2005Date of Patent: September 2, 2008Assignee: Inphi CorporationInventors: Prashant Choudhary, Venugopal Balasubramonian, Jishnu Bhattacharjee, Debanjan Mukherjee, Abhijit Phanse, Abhijit Shanbhag, Qian Yu
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Patent number: 7379495Abstract: An apparatus and method for adaptively introducing a compensating signal latency related to a signal latency of a data symbol decision circuit. Adaptive timing control circuitry, including an interpolating mixer implemented as a tapped delay line with correlated tap coefficients, introduces a latency adaptively and substantially matching the latency of the data decision circuit for use within an adaptive equalizer, thereby minimizing the mean-squared error of such decision circuit. This adaptive latency is used in generating the feedback error signal which, in turn, can be used by the feedforward equalizer for dynamically adjusting its adaptive filter tap coefficients.Type: GrantFiled: February 27, 2004Date of Patent: May 27, 2008Assignee: Scintera Networks Inc.Inventors: Qian Yu, Venugopal Balasubramonian, Jishnu Bhattacharjee, Debanjan Mukherjee, Abhijit Phanse, Abhijit G. Shanbhag, Edem Ibragimov, Fabian Giroud
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Publication number: 20080084850Abstract: A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.Type: ApplicationFiled: August 20, 2007Publication date: April 10, 2008Applicant: INFINEON TECHNOLOGIES AGInventors: Song Chen, Paul Chou, Christopher Woodthorpe, Venugopal Balasubramonian, Keith Rieken
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Patent number: 7339988Abstract: Systems and methods are disclosed to provide channel monitoring and/or performance monitoring for a communication channel. For example, in accordance with an embodiment of the present invention, an equalizer is disclosed that equalizes for channel distortions and also provides channel and performance monitoring information, such as for example bandwidth estimation, channel identification, signal-to-noise ratio, chromatic dispersion, and/or polarization-mode dispersion.Type: GrantFiled: July 3, 2003Date of Patent: March 4, 2008Assignee: Scintera Networks, Inc.Inventors: Abhijit G. Shanbhag, Abhijit Phanse, Jishnu Bhattacharjee, Debanjan Mukherjee, Prashant Choudhary, Edem Ibragimov, Venugopal Balasubramonian, Qian Yu, Madabusi Govindarajan
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Publication number: 20070230557Abstract: An adaptive signal equalizer with a feedforward filter in which the feedback error signal and corresponding incoming data signal are dynamically aligned in time using signal interpolation, and further, to control the precursor/postcursor filter taps configuration, thereby producing more adaptive filter tap coefficient signals for significantly improved and robust signal equalization.Type: ApplicationFiled: June 7, 2007Publication date: October 4, 2007Applicant: Scintera Networks, Inc.Inventors: Venugopal Balasubramonian, Jishnu Bhattacharjee, Edem Ibragimov, Debanjan Mukherjee, Abhijit Phanse, Abhijit Shanbhag, Qian Yu
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Patent number: 7266145Abstract: An adaptive signal equalizer with a feedforward filter in which the feedback error signal and corresponding incoming data signal are dynamically aligned in time using signal interpolation, and further, to control the precursor/postcursor filter taps configuration, thereby producing more adaptive filter tap coefficient signals for significantly improved and robust signal equalization.Type: GrantFiled: December 17, 2002Date of Patent: September 4, 2007Assignee: Scintera Networks, Inc.Inventors: Venugopal Balasubramonian, Jishnu Bhattacharjee, Edem Ibragimov, Debanjan Mukherjee, Abhijit Phanse, Abhijit G. Shanbhag, Qian Yu
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Patent number: 7203233Abstract: An adaptive coefficient signal generator for use in an adaptive signal equalizer with fractionally-spaced feedback. The signals representing the feedback tap coefficients are generated in conjunction with a timing interpolation parameter such that the fractionally-spaced feedback circuitry dynamically emulates symbol-spaced feedback circuitry.Type: GrantFiled: November 21, 2005Date of Patent: April 10, 2007Assignee: Scintera Networks, Inc.Inventors: Abhijit Shanbhag, Qian Yu, Abhijit Phanse, Jishnu Bhattacharjee, Debanjan Mukherjee, Fabian Giroud, Venugopal Balasubramonian