Patents by Inventor Veronica Aleman Strong
Veronica Aleman Strong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11942334Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the second thickness is different from the first thickness. In some embodiments, the first conductive trace and the second conductive trace have rectangular cross-sections.Type: GrantFiled: December 21, 2018Date of Patent: March 26, 2024Assignee: Intel CorporationInventors: Jeremy Ecton, Aleksandar Aleksov, Suddhasattwa Nad, Kristof Kuwawi Darmawikarta, Vahidreza Parichehreh, Veronica Aleman Strong, Xiaoying Guo
-
Publication number: 20240006292Abstract: Disclosed herein are via-trace-via structures with improved alignment, and related devices and methods. For example, in some embodiments, an integrated circuit (IC) package support may include a conductive structure having an aperture; a conductive via at least partially nested in the aperture in the conductive structure; and a conductive bridge spanning between and in contact with the conductive structure and the conductive via. In some embodiments, the conductive structure is a conductive pad. In some embodiments, the conductive structure is a conductive plane.Type: ApplicationFiled: July 1, 2022Publication date: January 4, 2024Applicant: Intel CorporationInventors: Veronica Aleman Strong, Aleksandar Aleksov
-
Patent number: 11784181Abstract: Embodiments may relate to a die with a front-end and a backend. The front-end may include a transistor. The backend may include a signal line, a conductive line, and a diode that is communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed.Type: GrantFiled: January 21, 2022Date of Patent: October 10, 2023Assignee: Intel CorporationInventors: Aleksandar Aleksov, Adel A. Elsherbini, Feras Eid, Veronica Aleman Strong, Johanna M. Swan
-
Patent number: 11749628Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the first microelectronic component is coupled to the second microelectronic component by interconnects, and wherein the interconnects include individual first metal contacts coupled to respective individual second metal contacts; and a void between an individual first metal contact that is not coupled to a respective individual second metal contact, wherein the void is in the first direct bonding region.Type: GrantFiled: November 9, 2022Date of Patent: September 5, 2023Assignee: Intel CorporationInventors: Adel A. Elsherbini, Veronica Aleman Strong, Shawna M. Lift, Brandon M. Rawlings, Jagat Shakya, Johanna M. Swan, David M. Craig, Jeremy Alan Streifer, Brennen Karl Mueller
-
Patent number: 11751367Abstract: Embodiments may relate to a microelectronic package comprising: a die and a package substrate coupled to the die with a first interconnect on a first face. The package substrate comprises: a second interconnect and a third interconnect on a second face opposite to the first face; a conductive signal path between the first interconnect and the second interconnect; a conductive ground path between the second interconnect and the third interconnect; and an electrostatic discharge (ESD) protection material coupled to the conductive ground path. The ESD protection material comprises a first electrically-conductive carbon allotrope having a first functional group, a second electrically-conductive carbon allotrope having a second functional group, and an electrically-conductive polymer chemically bonded to the first functional group and the second functional group permitting an electrical signal to pass between the first and second electrically-conductive carbon allotropes.Type: GrantFiled: September 7, 2021Date of Patent: September 5, 2023Assignee: Intel CorporationInventors: Veronica Aleman Strong, Johanna M. Swan, Aleksandar Aleksov, Adel A. Elsherbini, Feras Eid
-
Patent number: 11676918Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.Type: GrantFiled: February 22, 2022Date of Patent: June 13, 2023Assignee: Intel CorporationInventors: Adel A. Elsherbini, Feras Eid, Johanna M. Swan, Aleksandar Aleksov, Veronica Aleman Strong
-
Patent number: 11621236Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC package support may include: a first conductive structure; a second conductive structure; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a positive temperature coefficient material.Type: GrantFiled: December 27, 2019Date of Patent: April 4, 2023Assignee: Intel CorporationInventors: Feras Eid, Veronica Aleman Strong, Aleksandar Aleksov, Adel A. Elsherbini, Johanna M. Swan
-
Publication number: 20230074970Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the first microelectronic component is coupled to the second microelectronic component by interconnects, and wherein the interconnects include individual first metal contacts coupled to respective individual second metal contacts; and a void between an individual first metal contact that is not coupled to a respective individual second metal contact, wherein the void is in the first direct bonding region.Type: ApplicationFiled: November 9, 2022Publication date: March 9, 2023Applicant: Intel CorporationInventors: Adel A. Elsherbini, Veronica Aleman Strong, Shawna M. Liff, Brandon M. Rawlings, Jagat Shakya, Johanna M. Swan, David M. Craig, Jeremy Alan Streifer, Brennen Karl Mueller
-
Patent number: 11527501Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region and coupled to the first microelectronic component by the first and second direct bonding regions, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, and wherein individual first metal contacts in the first direct bonding region are coupled to respective individual second metal contacts in the second direct bonding region; and a void between an individual first metal contact and a respective individual second metal contact.Type: GrantFiled: December 15, 2020Date of Patent: December 13, 2022Assignee: Intel CorporationInventors: Adel A. Elsherbini, Veronica Aleman Strong, Shawna M. Liff, Brandon M. Rawlings, Jagat Shakya, Johanna M. Swan, David M. Craig, Jeremy Alan Streifer, Brennen Karl Mueller
-
Patent number: 11424239Abstract: Embodiments may relate to a package substrate that is to couple with the die. The package substrate may include a signal line that is communicatively coupled with the die. The package substrate may further include a conductive line. The package substrate may further include a diode communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed.Type: GrantFiled: December 21, 2019Date of Patent: August 23, 2022Assignee: Intel CorporationInventors: Aleksandar Aleksov, Adel A. Elsherbini, Feras Eid, Veronica Aleman Strong, Johanna M. Swan
-
Publication number: 20220181276Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.Type: ApplicationFiled: February 22, 2022Publication date: June 9, 2022Applicant: Intel CorporationInventors: Adel A. Elsherbini, Feras Eid, Johanna M. Swan, Aleksandar Aleksov, Veronica Aleman Strong
-
Patent number: 11348882Abstract: Embodiments may relate to a microelectronic package with an electrostatic discharge (ESD) protection structure within the package substrate. The ESD protection structure may include a cavity that has a contact of a signal line and a contact of a ground line positioned therein. Other embodiments may be described or claimed.Type: GrantFiled: November 13, 2019Date of Patent: May 31, 2022Assignee: Intel CorporationInventors: Aleksandar Aleksov, Feras Eid, Johanna M. Swan, Adel A. Elsherbini, Veronica Aleman Strong
-
Publication number: 20220149036Abstract: Embodiments may relate to a die with a front-end and a backend. The front-end may include a transistor. The backend may include a signal line, a conductive line, and a diode that is communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed.Type: ApplicationFiled: January 21, 2022Publication date: May 12, 2022Applicant: Intel CorporationInventors: Aleksandar Aleksov, Adel A. Elsherbini, Feras Eid, Veronica Aleman Strong, Johanna M. Swan
-
Patent number: 11296040Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.Type: GrantFiled: December 19, 2019Date of Patent: April 5, 2022Assignee: Intel CorporationInventors: Adel A. Elsherbini, Feras Eid, Johanna M. Swan, Aleksandar Aleksov, Veronica Aleman Strong
-
Publication number: 20220102270Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC component may include a conductive contact structure that includes a first contact element and a second contact element. The first contact element may be exposed at a face of the IC component, the first contact element may be between the face of the IC component and the second contact element, the second contact element may be spaced apart from the first contact element by a gap, and the second contact element may be in electrical contact with an electrical pathway in the IC component.Type: ApplicationFiled: December 13, 2021Publication date: March 31, 2022Applicant: Intel CorporationInventors: Adel A. Elsherbini, Feras Eid, Johanna M. Swan, Aleksandar Aleksov, Veronica Aleman Strong
-
Patent number: 11289431Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC component may include: a first conductive structure; a second conductive structure; and a material in contact with the first conductive structure and the second conductive structure, wherein the material has a first electrical conductivity before illumination of the material with optical radiation and a second electrical conductivity, different from the first electrical conductivity, after illumination of the material with optical radiation.Type: GrantFiled: December 27, 2019Date of Patent: March 29, 2022Assignee: Intel CorporationInventors: Feras Eid, Veronica Aleman Strong, Aleksandar Aleksov, Adel A. Elsherbini, Johanna M. Swan
-
Publication number: 20220093531Abstract: A switch in a package substrate of a microelectronic package is provided, the switch comprising: an actuator plate; a strike plate; and a connecting element mechanically coupling the actuator plate and the strike plate. The switch is configured to move within a cavity inside the package substrate between an open position and a closed position, a conductive material is coupled to the switch and to a ground via in the package substrate, and the conductive material is configured to move with the switch, such that the switch is conductively coupled to the ground via in the open position and the closed position.Type: ApplicationFiled: December 7, 2021Publication date: March 24, 2022Applicant: Intel CorporationInventors: Feras Eid, Veronica Aleman Strong, Aleksandar Aleksov, Adel A. Elsherbini, Johanna M. Swan
-
Patent number: 11264373Abstract: Embodiments may relate to a die with a front-end and a backend. The front-end may include a transistor. The backend may include a signal line, a conductive line, and a diode that is communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed.Type: GrantFiled: December 21, 2019Date of Patent: March 1, 2022Assignee: Intel CorporationInventors: Aleksandar Aleksov, Adel A. Elsherbini, Feras Eid, Veronica Aleman Strong, Johanna M. Swan
-
Patent number: 11239155Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC component may include a conductive contact structure that includes a first contact element and a second contact element. The first contact element may be exposed at a face of the IC component, the first contact element may be between the face of the IC component and the second contact element, the second contact element may be spaced apart from the first contact element by a gap, and the second contact element may be in electrical contact with an electrical pathway in the IC component.Type: GrantFiled: December 22, 2019Date of Patent: February 1, 2022Assignee: Intel CorporationInventors: Adel A. Elsherbini, Feras Eid, Johanna M. Swan, Aleksandar Aleksov, Veronica Aleman Strong
-
Patent number: 11222856Abstract: Embodiments may relate to a package substrate that includes a signal line and a ground line. The package substrate may further include a switch communicatively coupled with the ground line. The switch may have an open position where the switch is communicatively decoupled with the signal line, and a closed position where the switch is communicatively coupled with the signal line. Other embodiments may be described or claimed.Type: GrantFiled: December 19, 2019Date of Patent: January 11, 2022Assignee: Intel CorporationInventors: Feras Eid, Veronica Aleman Strong, Aleksandar Aleksov, Adel A. Elsherbini, Johanna M. Swan