Abstract: An isolation structure on an integrated circuit is formed using a shallow trench isolation process. A layer of buffer oxide is formed on a substrate. A layer of nitride is formed on the layer of buffer oxide. The layer of nitride and the layer of buffer oxide are patterned to form a trench area. An oxidation of the substrate is performed to provide for round corners at a perimeter of the trench area. The substrate is then etched to form a trench within the trench area.

Abstract: A method is presented in which nitrogen-based gas in incorporated in polysilicon gate re-oxidation to improve hot carrier performance. A gate oxide layer is formed. Gate material is deposited on the gate oxide layer. The gate material is etched to form a gate structure. The gate oxide layer and the gate are re-oxidized. During re-oxidation, nitrogen-based gas is introduced to nitridize re-oxidized portions of the gate oxide layer.

Abstract: A method and apparatus for reducing space allocation failures in a computer system that utilizes direct access storage devices to store data. The method comprises the steps of determining if authorization has been given to attempt to allocate an initial space request over more than one volume, and, if so, attempting to allocate space on a plurality of volumes. If the initial space request cannot be allocated on a plurality of volumes, the initial space request is reduced by a preset percentage, the five-extent limit is removed and an attempt is made to allocate the reduced space request on the plurality of volumes with the five extent limit removed. Alternatively, if authorization has not been given to attempt to allocate the initial space request over more than one volume, the initial space request is reduced by a preset percentage, the five-extent limit is removed and an attempt is made to allocate the reduced space request on a single volume.

Abstract: A method of forming CMOS transistors with self-aligned field regions. First and second spaced apart areas are provided on a silicon substrate. A masking member is formed protecting the first of said areas and exposing the second. The exposed area is doped with a p-type material which is driven in to form a p-well. The same region is again doped with additional p-type material after which the CMOS transistors are fabricated.