Patents by Inventor Victor Michael Griswold

Victor Michael Griswold has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4090239
    Abstract: An input/output system includes a plurality of modules and a system interface unit having a plurality of ports, each of which connects to a different one of the modules. The plurality of modules includes at least one processor and one memory module. The system interface unit includes a timer unit and a priority network for processing processor interrupt requests on a priority basis. The priority network connects to a register for storing coded priority level signals to be assigned to the different types of interrupt requests. The register is conditioned to store a low priority level for timer interrupts. The timer unit includes a preset register, an interval counter and a rollover counter. At the completion of each time interval, the interval counter is loaded automatically from the preset register and counting is continued. Simultaneously, the interval counter conditions the rollover counter to store a count registering the total number of completed intervals counted.
    Type: Grant
    Filed: December 30, 1976
    Date of Patent: May 16, 1978
    Assignee: Honeywell Information Systems Inc.
    Inventors: Jerome J. Twibell, Victor Michael Griswold, Jaime Calle
  • Patent number: 4080649
    Abstract: An input/output system couples to a host processor through a system interface unit and includes at least two input/output processing units and a memory unit. The system interface unit includes interrupt processing logic circuits for each input/output processing unit for processing interrupt requests on a priority basis. The system interface unit further includes a processor intercommunication network which connects to each of the interrupt processing logic circuits.The input/output operating system initiates an input/output operation in response to a connect interrupt generated by the host processor executing a connect instruction. The interrupt is directed to an assigned input/output processing unit by the System Interface Unit (SIU). The assigned processor executes an instruction sequence which causes an appropriate entry to be placed in an operating system queue located within the memory unit. The queue entry has sufficient data to specify the desired I/O operation.
    Type: Grant
    Filed: December 16, 1976
    Date of Patent: March 21, 1978
    Assignee: Honeywell Information Systems Inc.
    Inventors: Jaime Calle, Victor Michael Griswold