Abstract: In a technique for reducing the transconductance of an input stage of an operational amplifier, the phase delay which the active load current mirror introduces into the single path is utilized in a way such that the phase delay of the overall stage is less than the delay of the primary differential pair. It is a mathematical fact that when two sinusoidal signals of the same frequency are added together, the result is also sinusoidal. Considering two such signals, the second of which has a phase lag with respect to the first, if the two signals are combined by the addition of ordinates, the resulting sinusoid also has a phase lag. However, if the second signal is instead subtracted from the first, then the resulting sinusoid has a phase lead with resect to the first signal. The present invention makes use of this phenomenon by causing the delayed mirror signal to be subtracted from, rather than added to, the primary signal.

Abstract: A symmetric capture range is produced in a two-quadrant phase detector phase locked loop that utilizes nonsymmetric pulse waves. The phase detector is enabled only during VCO pulses. A latch stores the relative relationship between the leading edge of the input pulse and the center of the VCO pulse in the previous cycle. If the phase angle .theta. form the VCO pulse center to the leading edge of the input pulse is0 deg<.theta.<180 deg,then the phase detector incrementally decreases the VCO frequency at the next VCO pulse. If the phase angle .theta. is180 deg<.theta.<360 deg,then the phase detector incrementally increases the VCO frequency at the next VCO pulse.

Abstract: A Frequency-to-Voltage Convertor (FVC) circuit is based on a precision one-shot that is compensated in a way such that matching of transistors in the circuit is unimportant. Therefore, temperature spacial gradients are rejected. The necessary saturation voltages for the FVC's npn devices are compensated by modulating the drive level of these devices with temperature.

Abstract: A Frequency-to-Voltage Converter (FVC) circuit is based on a precision one-shot that is compensated in a way such that matching of transistors in the circuit is unimportant. Therefore, temperature spacial gradients are rejected. The necessary saturation voltages for the FVC's npn devices are compensated by modulating the drive level of these devices with temperature.

Abstract: A current mirror circuit includes four bipolar junction transistors. One transistor serves as an input device for conducting via its collector a majority of the reference current. Another transistor is connected as a compensation device, with its emitter connected to the base of the input device, its base connected to the collector of the input device for conducting a minority of the reference current, and its collector connected to conduct a portion of the output current. Two transistors are connected in cascode as output devices for conducting a portion of the output current. The first output device emitter and base are connected to the emitter and base, respectively, of the input device.