Abstract: A method is disclosed whereby identification information can be encoded onto a plurality of circuit dice on a wafer to enable each of them to be distinguished from one another. An array of electrically readable identification elements, such as resistors, is disposed on each of the circuit dice during the circuit fabrication process. A first mask is then positioned over the each of the dice which completely covers all but the identification elements. A step and repeat mask is then selectively positioned over a particular element or elements in the array which identify a circuit die by its location on the wafer. The die is then exposed using a conventional step and repeat photolithographic process so that only the selected identification element or elements in the array will remain. The second mask is then stepped over the next circuit die on the wafer but is positioned over a different identification element or elements in the array.

Abstract: A programmable circuit for inclusion in an integrated circuit die for encoding information identifying or otherwise relating to such die, such circuit utilizing a plurality of single bit information storage and reading bit cells, each bit cell including a MOSFET or IGFET capacitor structure as a bit storage element. A gate of the MOSFET or IGFET acts as a positive voltage plate of the capacitor, while a source and drain are both connected to ground and act as ground plates of the capacitor. Normally, an open circuit is present between the gate and the source and drain, however, when a programming high voltage is applied to the gate, the capacitor structure physically breaks down and a conduction path is formed between the gate and the source or drain. The presence or absence of this conduction path enables the MOSFET or IGFET capacitor structure to act as a binary bit.

Abstract: A test device (40) has a patterned conductive layer (42 or 44) particularly adapted for use in an E-beam probe system (FIG. 3) to study how local electric fields influence probe voltage measurements. The layer is composed of two or more conductors (A and B.sub.J C and D.sub.J) separated from each other. Each conductor has a group of fingers. The fingers (F1.sub.p, F0.sub.p, F2, F0.sub.Q and F1.sub.Q) run parallel to one another and are at least partially interdigitated. The width of each finger is constant along its length. The widths of the fingers and the spacings between them vary from finger to finger according to a selected pattern.