Patents by Inventor Victor Vartanian

Victor Vartanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070272952
    Abstract: An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.
    Type: Application
    Filed: August 10, 2007
    Publication date: November 29, 2007
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Voon-Yew Thean, Brian Goolsby, Linda McCormick, Bich-Yen Nguyen, Colita Parker, Mariam Sadaka, Victor Vartanian, Ted White, Melissa Zavala
  • Publication number: 20070241403
    Abstract: A substrate includes a first region and a second region. The first region comprises a III-nitride layer, and the second region comprises a first semiconductor layer. A first transistor (such as an n-type transistor) is formed in and on the III-nitride layer, and a second transistor (such as a p-type transistor) is formed in and on the first semiconductor layer. The III-nitride layer may be indium nitride. In the first region, the substrate may include a second semiconductor layer, a graded transition layer over the second semiconductor layer, and a buffer layer over the transition layer, where the III-nitride layer is over the buffer layer. In the second region, the substrate may include the second semiconductor layer and an insulating layer over the second semiconductor layer, where the first semiconductor layer is over the insulating layer.
    Type: Application
    Filed: April 12, 2006
    Publication date: October 18, 2007
    Inventors: Voon-Yew Thean, Bich-Yen Nguyen, Mariam Sadaka, Victor Vartanian, Ted White
  • Publication number: 20070210381
    Abstract: An electronic device can have an insulating layer lying between a first semiconductor layer and a base layer. A second semiconductor layer, having a different composition and stress as compared to the first semiconductor layer, can overlie at least a portion of the first semiconductor layer. In one embodiment, a first electronic component can include a first active region that includes a first portion of the first and the second semiconductor layers. A second electronic component can include a second active region that can include a second portion of the first semiconductor layer. Different processes can be used to form the electronic device. In another embodiment, annealing a workpiece can be performed and the stress of at least one of the semiconductor layers can be changed. In a different embodiment, annealing the workpiece can be performed either before or after the formation of the second semiconductor layer.
    Type: Application
    Filed: March 13, 2006
    Publication date: September 13, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Mariam Sadaka, Venkat Kolagunta, William Taylor, Victor Vartanian
  • Publication number: 20070108481
    Abstract: An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.
    Type: Application
    Filed: November 14, 2005
    Publication date: May 17, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Voon-Yew Thean, Brian Goolsby, Linda McCormick, Bich-Yen Nguyen, Colita Parker, Mariam Sadaka, Victor Vartanian, Ted White, Melissa Zavala
  • Publication number: 20060183288
    Abstract: An impurity can be introduced into a semiconductor layer of a workpiece to affect the oxidation and the relative concentration of one element with respect to another element within the semiconductor layer. The impurity can be selectively implanted using one or more masks, manipulating the beam line of an ion implant tool, moving a workpiece relative to the ion beam, or the like. The dose can vary as a function of distance from the center of the workpiece or vary locally based on the design of the electronic device or desires of the electronic device fabricator. In one embodiment, the impurity can be implanted in such a way as to result in a more uniform SiGe condensation across the substrate or across one or more portions of the substrate when the semiconductor layer includes a SiGe layer.
    Type: Application
    Filed: February 15, 2005
    Publication date: August 17, 2006
    Inventors: Marius Orlowski, Victor Vartanian
  • Publication number: 20060065927
    Abstract: A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.
    Type: Application
    Filed: September 29, 2004
    Publication date: March 30, 2006
    Inventors: Voon-Yew Thean, Mariam Sadaka, Ted White, Alexander Barr, Venkat Kolagunta, Bich-Yen Nguyen, Victor Vartanian, Da Zhang
  • Publication number: 20060068553
    Abstract: A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.
    Type: Application
    Filed: September 29, 2004
    Publication date: March 30, 2006
    Inventors: Voon-Yew Thean, Mariam Sadaka, Ted White, Alexander Barr, Venkat Kolagunta, Bich-Yen Nguyen, Victor Vartanian, Da Zhang