Patents by Inventor Victor Zyuban

Victor Zyuban has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210376831
    Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.
    Type: Application
    Filed: August 11, 2021
    Publication date: December 2, 2021
    Inventors: Keith Cox, Victor Zyuban, Norman J. Rohrer
  • Patent number: 11152046
    Abstract: A memory array that provides an internal retention voltage without a voltage regulator is disclosed. The memory array includes a first group of bit cells coupled between the power supply rail and a ground switch and a second group of bit cells coupled to a retention select circuit. The retention select circuit is coupled to the ground for the first group of bit cells and the power supply rail. The ground switch and the retention select circuit may be operated to switch the bit cells between a nominal operating voltage and a retention voltage. The retention voltage is provided during inactive periods of the memory array to maintain data in the bit cells during the inactive periods.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: October 19, 2021
    Assignee: Apple Inc.
    Inventors: Jaroslav Raszka, Shahzad Nazar, Jaemyung Lim, Mohamed H. Abu-Rahma, Victor Zyuban
  • Patent number: 11121711
    Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: September 14, 2021
    Assignee: Apple Inc.
    Inventors: Keith Cox, Victor Zyuban, Norman J. Rohrer
  • Publication number: 20210250019
    Abstract: A system and method for efficiently retaining data in sequential elements during power down modes. In various embodiments, a master latch of a flip-flop circuit receives an always-on first power supply voltage, whereas, a slave latch and other surrounding circuitry receives a second power supply voltage capable of being powered down. During a power down mode, circuitry consumes less power while the master latch retains stored data. In some designs, the flip-flop circuit is a level shifting circuit, and the always-on first power supply voltage is less than the second power supply voltage. The master latch uses complex gates with a p-type transistor at the top of a stack of p-type transistors receiving the always-on power supply voltage level on its source terminal and the retained data value on its gate terminal. This top p-type transistor is capable of remaining disabled even when used in a level shifting manner.
    Type: Application
    Filed: April 30, 2021
    Publication date: August 12, 2021
    Inventors: Greg M. Hess, Vivekanandan Venugopal, Victor Zyuban
  • Patent number: 11005459
    Abstract: A system and method for efficiently retaining data in sequential elements during power down modes. In various embodiments, a master latch of a flip-flop circuit receives an always-on first power supply voltage, whereas, a slave latch and other surrounding circuitry receives a second power supply voltage capable of being powered down. During a power down mode, circuitry consumes less power while the master latch retains stored data. In some designs, the flip-flop circuit is a level shifting circuit, and the always-on first power supply voltage is less than the second power supply voltage. The master latch uses complex gates with a p-type transistor at the top of a stack of p-type transistors receiving the always-on power supply voltage level on its source terminal and the retained data value on its gate terminal. This top p-type transistor is capable of remaining disabled even when used in a level shifting manner.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 11, 2021
    Assignee: Apple Inc.
    Inventors: Greg M. Hess, Vivekanandan Venugopal, Victor Zyuban
  • Patent number: 10908663
    Abstract: A power switch multiplexer with configurable overlap is disclosed. An integrated circuit (IC) includes a first functional circuit block coupled to receive a supply voltage from a first supply voltage node. The IC further includes an input circuit and an output circuit. Responsive to receiving an input signal, the input circuit asserts an activation signal to cause one of a second supply voltage node and a third supply voltage node to be electrically coupled to the first supply voltage node. Subsequently the input circuit asserts a deactivation signal to cause the other one of the second and third supply voltage nodes to be electrically decoupled from the first supply voltage node. The output circuit is coupled to receive the activation signal and the deactivation signal, and configured to assert a first output signal subsequent to receiving the activation signal.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: February 2, 2021
    Assignee: Apple Inc.
    Inventors: Victor Zyuban, Greg M. Hess, Hemangi U. Gajjewar
  • Publication number: 20210028785
    Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.
    Type: Application
    Filed: August 31, 2020
    Publication date: January 28, 2021
    Inventors: Keith Cox, Victor Zyuban, Norman J. Rohrer
  • Publication number: 20200387205
    Abstract: A power switch multiplexer with configurable overlap is disclosed. An integrated circuit (IC) includes a first functional circuit block coupled to receive a supply voltage from a first supply voltage node. The IC further includes an input circuit and an output circuit. Responsive to receiving an input signal, the input circuit asserts an activation signal to cause one of a second supply voltage node and a third supply voltage node to be electrically coupled to the first supply voltage node. Subsequently the input circuit asserts a deactivation signal to cause the other one of the second and third supply voltage nodes to be electrically decoupled from the first supply voltage node. The output circuit is coupled to receive the activation signal and the deactivation signal, and configured to assert a first output signal subsequent to receiving the activation signal.
    Type: Application
    Filed: June 6, 2019
    Publication date: December 10, 2020
    Inventors: Victor Zyuban, Greg M. Hess, Hemangi U. Gajjewar
  • Patent number: 10763859
    Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: September 1, 2020
    Assignee: Apple Inc.
    Inventors: Keith Cox, Victor Zyuban, Norman J. Rohrer
  • Publication number: 20200162077
    Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.
    Type: Application
    Filed: November 18, 2019
    Publication date: May 21, 2020
    Inventors: Keith Cox, Victor Zyuban, Norman J. Rohrer
  • Patent number: 10599207
    Abstract: A method and apparatus for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes inhibiting one or more processor cores from exiting an idle state. The method further includes determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores. The method also includes selecting a maximum frequency for the inhibited processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores. The method includes setting the maximum frequency for the inhibited processor cores, and then uninhibiting the processor cores requesting exit from the idle state.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Charles R. Lefurgy, Karthick Rajamani, Todd J. Rosedahl, Guillermo J. Silva, Gregory S. Still, Victor Zyuban
  • Patent number: 10523194
    Abstract: A power switch control circuit is disclosed. A sensor circuit may determine a leakage current of a power switch coupled to a power supply signal and a power terminal of a circuit block. The power switch may be configured to selectively couple or decouple the circuit block from the power supply signal using a switch control signal. The switch control circuit may, in response to receiving a request to open the power switch, determine a target voltage level that is greater than a voltage level of the power supply signal for the switch control signal using the leakage current, and transition the switch control signal from an initial voltage to the target voltage level.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: December 31, 2019
    Assignee: Apple Inc.
    Inventors: Jaroslav Raszka, Amrinder S. Barn, Victor Zyuban, Shingo Suzuki, Ajay Kumar Bhatia, Mohamed H. Abu-Rahma, Shahzad Nazar, Greg M. Hess
  • Patent number: 10483974
    Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: November 19, 2019
    Assignee: Apple Inc.
    Inventors: Keith Cox, Victor Zyuban, Norman J. Rohrer
  • Publication number: 20190097622
    Abstract: A power switch control circuit is disclosed. A sensor circuit may determine a leakage current of a power switch coupled to a power supply signal and a power terminal of a circuit block. The power switch may be configured to selectively couple or decouple the circuit block from the power supply signal using a switch control signal. The switch control circuit may, in response to receiving a request to open the power switch, determine a target voltage level that is greater than a voltage level of the power supply signal for the switch control signal using the leakage current, and transition the switch control signal from an initial voltage to the target voltage level.
    Type: Application
    Filed: September 27, 2017
    Publication date: March 28, 2019
    Inventors: Jaroslav Raszka, Amrinder S. Barn, Victor Zyuban, Shingo Suzuki, Ajay Kumar Bhatia, Mohamed H. Abu-Rahma, Shahzad Nazar, Greg M. Hess
  • Publication number: 20190052271
    Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.
    Type: Application
    Filed: September 24, 2018
    Publication date: February 14, 2019
    Inventors: Keith Cox, Victor Zyuban, Norman J. Rohrer
  • Patent number: 10187045
    Abstract: Techniques are disclosed relating to dual-edge triggered (DET) clock gater circuitry. In some embodiments, an apparatus includes a first series of DET clock gater circuits configured, when the DET clock gater circuits are not gating an input clock signal, to provide an output clock signal to sequential circuitry. In some embodiments, ones of the DET clock gater circuits are controlled by respective control signals and are configured to maintain a mode indicator indicating whether or not the DET clock gater circuit is inverting the polarity of its input clock when generating an output clock. In some embodiments, the apparatus also includes a first adjustable delay circuit configured to adjust delay imposed on the output clock signal from the first series of DET clock gater circuits based on the number of DET clock gater circuits in the series that are in a particular mode.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: January 22, 2019
    Assignee: Apple Inc.
    Inventors: Victor Zyuban, Norman Rohrer, Nimish Kabe, Neela Lohith Penmetsa
  • Patent number: 10084450
    Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: September 25, 2018
    Assignee: Apple Inc.
    Inventors: Keith Cox, Victor Zyuban, Norman J Rohrer
  • Patent number: 9971393
    Abstract: The embodiments described herein relate to dynamically detecting a frequency change condition for microprocessor performance. An instruction is received, and a frequency change condition associated with the received instruction is dynamically detected. A frequency modulation is performed in response to the dynamic detection. The frequency modulation includes selecting a second frequency for optimal instruction processing different from a first frequency, the first frequency being a default operating frequency of the microprocessor. Execution of the instruction is completed at the second frequency. Accordingly, incoming execution instructions are logically analyzed, and the processor frequency is selectively modified based on associated instruction conditions.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bjorn P. Christensen, Victor Zyuban
  • Patent number: 9952651
    Abstract: A system for adjusting a frequency of a processor is disclosed herein. The system includes a processor and a memory, where the memory includes a program configured to adjust a frequency of a multi-core processor. The operations include determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The operations also include calculating a switching current by subtracting the leakage current from the total current and calculating an effective switching capacitance based at least in part on the switching current. The operations also include calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: April 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Malcolm S. Allen-Ware, Michael S. Floyd, Joshua D. Friedrich, Charles R. Lefurgy, Kirk D. Peterson, Karthick Rajamani, Srinivasan Ramani, Todd J. Rosedahl, Gregory S. Still, Brian W. Thompto, Victor Zyuban
  • Publication number: 20180101217
    Abstract: A method and apparatus for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes inhibiting one or more processor cores from exiting an idle state. The method further includes determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores. The method also includes selecting a maximum frequency for the inhibited processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores. The method includes setting the maximum frequency for the inhibited processor cores, and then uninhibiting the processor cores requesting exit from the idle state.
    Type: Application
    Filed: December 7, 2017
    Publication date: April 12, 2018
    Inventors: Malcolm S. ALLEN-WARE, Charles R. LEFURGY, Karthick RAJAMANI, Todd J. ROSEDAHL, Guillermo J. SILVA, Gregory S. STILL, Victor ZYUBAN