Patents by Inventor Vidya Rajagopalan
Vidya Rajagopalan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150293853Abstract: A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way prediction value and forwards the data to dependent instructions before a physical address for the data is available. After the physical address is available, the physical address is compared to a physical address tag value for the forwarded data to verify that the forwarded data is the correct data. If the forwarded data is the correct data, a hit signal is generated. If the forwarded data is not the correct data, a miss signal is generated. Any instructions that operate on incorrect data are invalidated and/or replayed.Type: ApplicationFiled: June 25, 2015Publication date: October 15, 2015Inventors: Meng-Bing Yu, Era K. Nangia, Michael Ni, Vidya Rajagopalan
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Patent number: 9092343Abstract: A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way prediction value and forwards the data to dependent instructions before a physical address for the data is available. After the physical address is available, the physical address is compared to a physical address tag value for the forwarded data to verify that the forwarded data is the correct data. If the forwarded data is the correct data, a hit signal is generated. If the forwarded data is not the correct data, a miss signal is generated. Any instructions that operate on incorrect data are invalidated and/or replayed.Type: GrantFiled: September 21, 2009Date of Patent: July 28, 2015Assignee: ARM Finance Overseas LimitedInventors: Meng-Bing Yu, Era K. Nangia, Michael Ni, Vidya Rajagopalan
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Patent number: 8078846Abstract: A conditional move instruction implemented in a processor by forming and processing two decoded instructions, and applications thereof. In an embodiment, the conditional move instruction specifies a first source operand, a second source operand, and a third operand that is both a source and a destination. If the value of the second operand is not equal to a specified value, the first decoded instruction moves the third operand to a completion buffer register. If the value of the second operand is equal to the specified value, the second decoded instruction moves the value of the first operand to the completion buffer. When the decoded instruction that performed the move graduates, the contents of the completion buffer register is transferred to a register file register specified by the third operand.Type: GrantFiled: December 18, 2006Date of Patent: December 13, 2011Assignee: MIPS Technologies, Inc.Inventors: Karagada Ramarao Kishore, Xing Yu Jiang, Vidya Rajagopalan, Maria Ukanwa
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Patent number: 7721075Abstract: A RISC processor having a data mover engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instruction. The read-tie, single write-tie, and dual write-tie instructions are used to associate software accessible register addresses with memory addresses. These associations effect the operation of the data mover engine such that, for the duration of the associations, the data mover engine routes data to and from associated memory addresses and the execution unit of the processor in response to instructions that specify moving data to and from the associated register addresses. The invention reduces the number of instructions and hardware overhead associated with implementing program loops in a RISC processor.Type: GrantFiled: January 23, 2006Date of Patent: May 18, 2010Assignee: MIPS Technologies, Inc.Inventors: Radhika Thekkath, Karagada Ramarao Kishore, Vidya Rajagopalan, Kevin D. Kissell
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Patent number: 7711934Abstract: A processor core and method for managing branch misprediction in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch portion, a back-end instruction execution portion, and pipeline control logic. Operation of the instruction fetch portion is decoupled from operation of the instruction execution portion. Following detection of a control transfer misprediction, operation of the instruction fetch portion is halted and instructions residing in the instruction fetch portion are invalidated. When the instruction associated with the misprediction reaches a selected pipeline stage, instructions residing in the instruction execution portion of the pipeline are invalidated and the flow of instructions from the instruction fetch portion to the instruction execution portion of the processor pipeline is restarted.Type: GrantFiled: October 31, 2005Date of Patent: May 4, 2010Assignee: MIPS Technologies, Inc.Inventors: Karagada Ramarao Kishore, Kjeld Svendsen, Vidya Rajagopalan
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Publication number: 20100011166Abstract: A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way prediction value and forwards the data to dependent instructions before a physical address for the data is available. After the physical address is available, the physical address is compared to a physical address tag value for the forwarded data to verify that the forwarded data is the correct data. If the forwarded data is the correct data, a hit signal is generated. If the forwarded data is not the correct data, a miss signal is generated. Any instructions that operate on incorrect data are invalidated and/or replayed.Type: ApplicationFiled: September 21, 2009Publication date: January 14, 2010Applicant: MIPS Technologies, Inc.Inventors: Meng-Bing YU, Era K. NANGIA, Michael NI, Vidya RAJAGOPALAN
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Patent number: 7594079Abstract: A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way prediction value and forwards the data to dependent instructions before a physical address for the data is available. After the physical address is available, the physical address is compared to a physical address tag value for the forwarded data to verify that the forwarded data is the correct data. If the forwarded data is the correct data, a hit signal is generated. If the forwarded data is not the correct data, a miss signal is generated. Any instructions that operate on incorrect data are invalidated and/or replayed.Type: GrantFiled: October 11, 2006Date of Patent: September 22, 2009Assignee: MIPS Technologies, Inc.Inventors: Meng-Bing Yu, Era K. Nangia, Michael Ni, Vidya Rajagopalan
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Publication number: 20080082795Abstract: A conditional move instruction implemented in a processor by forming and processing two decoded instructions, and applications thereof. In an embodiment, the conditional move instruction specifies a first source operand, a second source operand, and a third operand that is both a source and a destination. If the value of the second operand is not equal to a specified value, the first decoded instruction moves the third operand to a completion buffer register. If the value of the second operand is equal to the specified value, the second decoded instruction moves the value of the first operand to the completion buffer. When the decoded instruction that performed the move graduates, the contents of the completion buffer register is transferred to a register file register specified by the third operand.Type: ApplicationFiled: December 18, 2006Publication date: April 3, 2008Applicant: MIPS Technologies, Inc.Inventors: Karagada Ramarao Kishore, Xing Yu Jiang, Vidya Rajagopalan, Maria Ukanwa
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Publication number: 20080082721Abstract: A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way prediction value and forwards the data to dependent instructions before a physical address for the data is available. After the physical address is available, the physical address is compared to a physical address tag value for the forwarded data to verify that the forwarded data is the correct data. If the forwarded data is the correct data, a hit signal is generated. If the forwarded data is not the correct data, a miss signal is generated. Any instructions that operate on incorrect data are invalidated and/or replayed.Type: ApplicationFiled: October 11, 2006Publication date: April 3, 2008Applicant: MIPS Technologies, Inc.Inventors: Meng-Bing Yu, Era K. Nangia, Michael Ni, Vidya Rajagopalan
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Publication number: 20070174595Abstract: A RISC processor having a data mover engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instruction. The read-tie, single write-tie, and dual write-tie instructions are used to associate software accessible register addresses with memory addresses. These associations effect the operation of the data mover engine such that, for the duration of the associations, the data mover engine routes data to and from associated memory addresses and the execution unit of the processor in response to instructions that specify moving data to and from the associated register addresses. The invention reduces the number of instructions and hardware overhead associated with implementing program loops in a RISC processor.Type: ApplicationFiled: January 23, 2006Publication date: July 26, 2007Applicant: MIPS Technologies, Inc.Inventors: Radhika Thekkath, Karagada Kishore, Vidya Rajagopalan
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Publication number: 20070101110Abstract: A processor core and method for managing branch misprediction in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch portion, a back-end instruction execution portion, and pipeline control logic. Operation of the instruction fetch portion is decoupled from operation of the instruction execution portion. Following detection of a control transfer misprediction, operation of the instruction fetch portion is halted and instructions residing in the instruction fetch portion are invalidated. When the instruction associated with the misprediction reaches a selected pipeline stage, instructions residing: in the instruction execution portion of the pipeline are invalidated and the flow of instructions from the instruction fetch portion to the instruction execution portion of the processor pipeline is restarted.Type: ApplicationFiled: October 31, 2005Publication date: May 3, 2007Applicant: MIPS Technologies, Inc.Inventors: Karagada Kishore, Kjeld Svendsen, Vidya Rajagopalan
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Publication number: 20070089095Abstract: A system and method for program counter and data tracing in a multi-issue processor is disclosed. Instructions are traced in program sequence order. In one embodiment instructions are traced in graduation order from a reorder buffer. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.Type: ApplicationFiled: December 8, 2006Publication date: April 19, 2007Applicant: MIPS TECHNOLOGIES, INC.Inventors: Radhika Thekkath, Franz Treue, Soren Kragh, Vidya Rajagopalan
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Patent number: 7159101Abstract: A system and method for program counter and data tracing in a multi-issue processor is disclosed. Instructions are traced in program sequence order. In one embodiment instructions are traced in graduation order from a reorder buffer. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.Type: GrantFiled: May 28, 2003Date of Patent: January 2, 2007Assignee: MIPS Technologies, Inc.Inventors: Radhika Thekkath, Franz Treue, Søren Kragh, Vidya Rajagopalan
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Patent number: 7124072Abstract: A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.Type: GrantFiled: April 30, 2001Date of Patent: October 17, 2006Assignee: MIPS Technologies, Inc.Inventors: Radhika Thekkath, George Michael Uhler, Franz Treue, Lawrence Henry Hudepohl, Vidya Rajagopalan
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Patent number: 6732208Abstract: A bus interface to a split transaction computing bus having separate address and data portions is provided. The bus interface contains separate address and data interfaces for initiating and tracking out-of-order transactions on either or both of the address or data portions of the computing bus. The bus interface includes split transaction tracking and control to establish transaction ID's for each transaction initiated by the bus interface, and to determine whether data appearing on the data portion of the computing bus is associated with one of its pending transactions. The bus interface also contains flow control logic to determine whether devices that are to be read from, or written to, by the bus interface, have resources (buffers) available to respond to the transactions. If the resources are available, the flow control logic allows the transactions to proceed, and adjusts its counters to reflect the use of the resources.Type: GrantFiled: May 27, 1999Date of Patent: May 4, 2004Assignee: MIPS Technologies, Inc.Inventors: Adel M. Alsaadi, Vidya Rajagopalan
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Patent number: 6493776Abstract: An on-chip split transaction system bus having separate address and data portions is provided. The system bus contains separate address and data buses for initiating and tracking out-of-order transactions on either or both of the address or data portions of the bus. The system bus provides communication via a bus interface that includes split transaction tracking and control to establish transaction ID's for each transaction initiated by the bus interface, and to determine whether data appearing on the data portion of the system bus is associated with one of its pending transactions. The bus interface also contains flow control logic to determine whether devices that are to be read from, or written to, by the bus interface, have resources (buffers) available to respond to the transactions. If the resources are available, the flow control logic allows the transactions to proceed, and adjusts its counters to reflect the use of the resources.Type: GrantFiled: August 12, 1999Date of Patent: December 10, 2002Assignee: MIPS Technologies, Inc.Inventors: David A. Courtright, Vidya Rajagopalan, Radhika Thekkath, G. Michael Uhler
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Patent number: 5341319Abstract: A floating point multiply of two n-bit operands creams a 2n-bit result, but ordinarily only n-bit precision is needed, so rounding is performed. Some rounding algorithms require the knowledge of the presence of any "1" in the n-2 low-order bits of the 2n-bit result. The presence of such a "1", indicates the so-called "sticky bit" is set. The sticky bit is calculated in a path separate from the multiply operation, so the n-2 least significant sums need not be calculated. This saves time and circuitry in an array multiplier, for example. In an example method, the difference between n and the number of trailing zeros, "x", in one of the n-bit operands is detected, by transposing the operand and detecting the leading one. The other operand is right-shifted by a number of bit positions equal to this difference. A sticky bit is generated if any logic "1's" are in the low-order n-x-2 bits fight shifted out of the second operand.Type: GrantFiled: February 10, 1993Date of Patent: August 23, 1994Assignee: Digital Equipment CorporationInventors: William C. Madden, Vidya Rajagopalan, Sridhar Samudrala
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Patent number: 5155382Abstract: A master/slave latch circuit employs a single-wire clock, with the clock being applied to only N-channel transistors in the master latch and to only P-channel transistors in the slave latch so that a race-through condition is alleviated in the event of clock skew. The circuits are of ratioless operation, since P-channel transistors are used in each circuit to pull the high side to the supply voltage, and N-channel transistors are used on the low side to assure a zero voltage level. Input to each latch is to the gates of a P-channel pull-up and an N-channel pull-down, while the storage node is between the two clocked transistors. The level of the storage node is inverted and fed back to at transistor across one of the clocked transistors, the one on the high side for the master latch and the low side for the slave latch, and these feedback transistors are of a channel type to support the ratioless scheme.Type: GrantFiled: February 7, 1992Date of Patent: October 13, 1992Assignee: Digital Equipment CorporationInventors: William C. Madden, Vidya Rajagopalan