Patents by Inventor Vijay Bahirji

Vijay Bahirji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220262427
    Abstract: A mechanism where the locked pages are saved and restored by a hardware accelerator which is transparent to the OS. Prior to standby entry, the OS puts all DMA capable devices in the lowest-powered device low-power state after disabling bus mastering. The OS flushes all pageable memory to an NVM (in segments that are kept in self-refresh) and provides a list of pinned and locked pages in the DRAM to a power management controller (p-unit). The p-unit checks for all Bus Mastering DMA to be turned off and checks if a next OS timer wake event (TNTE) is greater than a threshold, to decide whether to enable or disable PASR or MPSM in Standby. If the conditions are met, the p-unit triggers a hardware accelerator to consolidate the pinned and locked pages in the DRAM to certain segment(s) of the DRAM during standby states, making it transparent to the OS.
    Type: Application
    Filed: February 17, 2021
    Publication date: August 18, 2022
    Applicant: Intel Corporation
    Inventors: Nivedha Krishnakumar, Virendra Vikramsinh Adsure, Jaya Jeyaseelan, Nadav Bonen, Barnes Cooper, Toby Opferman, Vijay Bahirji, Chia-Hung Kuo
  • Publication number: 20210245046
    Abstract: Described herein is a cloud-based gaming system in which graphics processing operations of a cloud-based game can be performed on a client device. Client-based graphics processing can be enabled in response to a determination that the client includes a graphics processor having a performance that exceeds a minimum threshold. When a game is remotely executed and streamed to a client, the client is configurable to provide network feedback that can be used to adjust execution and/or encoding for the game.
    Type: Application
    Filed: February 5, 2021
    Publication date: August 12, 2021
    Applicant: Intel Corporation
    Inventors: MAKARAND DHARMAPURIKAR, RAJABALI KODURI, VIJAY BAHIRJI, TOBY OPFERMAN, SCOTT G. CHRISTIAN, RAJEEV PENMATSA, SELVAKUMAR PANNEER
  • Publication number: 20210019260
    Abstract: Systems, apparatuses and methods may provide for technology that identifies a NUMA node, defines a first virtual proximity domain within the NUMA node, and defines a second virtual proximity domain within the NUMA node, wherein the first virtual proximity domain and the second virtual proximity domain are defined via one or more OS interface tables.
    Type: Application
    Filed: August 6, 2020
    Publication date: January 21, 2021
    Inventors: Kyle Delehanty, Sridharan Sakthivelu, Janardhana Yoga Narasimhaswamy, Vijay Bahirji, Toby Opferman
  • Patent number: 10733108
    Abstract: A system for computer memory management that implements a memory pool table, the memory pool table including entries that describe a plurality of memory pools, each memory pool representing a group of memory pages related by common attributes; a per-page tracking table, each entry in the per-page tracking table used to related a memory page with a memory pool of the memory pool table; and processing circuitry to: scan each entry in the per-page tracking table and, for each entry: determine an amount of memory released if the memory page related with the entry is swapped; aggregate the amount of memory for the respective memory pool related with the memory page related with the entry in the per-page tracking table, to produce a per-pool memory aggregate; and output the per-pool memory aggregate for the memory pools related with the memory pages in the per-page tracking table.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Vijay Bahirji, Amin Firoozshahian, Mahesh Madhav, Toby Opferman, Omid Azizi
  • Publication number: 20190354487
    Abstract: A system for computer memory management that implements a memory pool table, the memory pool table including entries that describe a plurality of memory pools, each memory pool representing a group of memory pages related by common attributes; a per-page tracking table, each entry in the per-page tracking table used to related a memory page with a memory pool of the memory pool table; and processing circuitry to: scan each entry in the per-page tracking table and, for each entry: determine an amount of memory released if the memory page related with the entry is swapped; aggregate the amount of memory for the respective memory pool related with the memory page related with the entry in the per-page tracking table, to produce a per-pool memory aggregate; and output the per-pool memory aggregate for the memory pools related with the memory pages in the per-page tracking table.
    Type: Application
    Filed: May 15, 2018
    Publication date: November 21, 2019
    Inventors: Vijay Bahirji, Amin Firoozshahian, Mahesh Madhav, Toby Opferman, Omid Azizi