Abstract: A hot-plugged PCIe device configuration system includes a PCIe device with a PCIe configuration space having PCIe configuration space registers. A computing system includes a PCIe connector and a PCIe setting record database storing a first PCIe setting record having a first register write location value and first register value information. The computing system detects that the PCIe device has been hot-plugged into the PCIe connector, and uses the first register write location value in the first PCIe setting record to determine a location in the PCIe configuration space that provides a first PCIe configuration space register. The computing system then uses the first register value information in the first PCIe setting record to determine at least one register value change for the first PCIe configuration register, and writes the at least one register value change to the first PCIe configuration space register using the location.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor, a memory communicatively coupled to the processor and comprising a plurality of non-volatile memories, and a failure analysis module comprising a program of instructions, the failure analysis module configured to, when read and executed by the processor, set a predictive failure threshold for each of the plurality of non-volatile memories based at least on functional parameters of such non-volatile memory, and adapt the predictive failure threshold for each of the plurality of non-volatile memories based at least on health status parameters of such non-volatile memory.

Abstract: A method, and systems and articles of manufacture for performing the method, may be provided for use in an information handling system comprising one or more processors and a memory system communicatively coupled to the one or more processors. The method may include enumerating memory modules of the memory system and installing a concurrent firmware protocol to each of the memory modules, wherein the concurrent firmware protocol is configured to individually execute an update routine on each of the memory modules. The update routine may be configured to, on each memory module, store a to-be-applied firmware update in a protected non-volatile region of the memory module and pull the to-be-applied firmware update from the protected non-volatile region of the memory module and perform a self-update of firmware for the memory module.

Abstract: A hot-plugged PCIe device configuration system includes a PCIe device with a PCIe configuration space having PCIe configuration space registers. A computing system includes a PCIe connector and a PCIe setting record database storing a first PCIe setting record having a first register write location value and first register value information. The computing system detects that the PCIe device has been hot-plugged into the PCIe connector, and uses the first register write location value in the first PCIe setting record to determine a location in the PCIe configuration space that provides a first PCIe configuration space register. The computing system then uses the first register value information in the first PCIe setting record to determine at least one register value change for the first PCIe configuration register, and writes the at least one register value change to the first PCIe configuration space register using the location.

Abstract: An information handling system includes an I/O device, a first processor die coupled to the I/O device, a second processor die coupled to the first processor die, and to no I/O device, and boot process logic. The boot process logic determines that the first processor die is coupled to the I/O device and that the second processor die is coupled to no I/O device, determines that an operating environment of the information handling system is capable of utilizing a maximum of Z processor cores, where Z is an integer number that is greater than X and less than the sum of X+Y, and enables Z processor cores on the first and second processor dies by enabling the X processor cores on the first processor die, and enabling the remainder of cores, equal to Z?X, on the second processor die, based upon the determination that the second processor die is coupled to no I/O device.

Abstract: A hot-plugged PCIe device configuration system includes a PCIe device with a PCIe configuration space having PCIe configuration space registers. A computing system includes a PCIe connector and a PCIe setting record database storing a first PCIe setting record having a first register write location value and first register value information. The computing system detects that the PCIe device has been hot-plugged into the PCIe connector, and uses the first register write location value in the first PCIe setting record to determine a location in the PCIe configuration space that provides a first PCIe configuration space register. The computing system then uses the first register value information in the first PCIe setting record to determine at least one register value change for the first PCIe configuration register, and writes the at least one register value change to the first PCIe configuration space register using the location.

Abstract: An information handling system includes an I/O device, a first processor die coupled to the I/O device, a second processor die coupled to the first processor die, and to no I/O device, and boot process logic. The boot process logic determines that the first processor die is coupled to the I/O device and that the second processor die is coupled to no I/O device, determines that an operating environment of the information handling system is capable of utilizing a maximum of Z processor cores, where Z is an integer number that is greater than X and less than the sum of X+Y, and enables Z processor cores on the first and second processor dies by enabling the X processor cores on the first processor die, and enabling the remainder of cores, equal to Z?X, on the second processor die, based upon the determination that the second processor die is coupled to no I/O device.

Abstract: A method, and systems and articles of manufacture for performing the method, may be provided for use in an information handling system comprising one or more processors and a memory system communicatively coupled to the one or more processors. The method may include enumerating memory modules of the memory system and installing a concurrent firmware protocol to each of the memory modules, wherein the concurrent firmware protocol is configured to individually execute an update routine on each of the memory modules. The update routine may be configured to, on each memory module, store a to-be-applied firmware update in a protected non-volatile region of the memory module and pull the to-be-applied firmware update from the protected non-volatile region of the memory module and perform a self-update of firmware for the memory module.

Abstract: An information handling system includes an I/O device, a first processor die coupled to the I/O device, a second processor die coupled to the first processor die, and to no I/O device, and boot process logic. The boot process logic determines that the first processor die is coupled to the I/O device and that the second processor die is coupled to no I/O device, determines that an operating environment of the information handling system is capable of utilizing a maximum of Z processor cores, where Z is an integer number that is greater than X and less than the sum of X+Y, and enables Z processor cores on the first and second processor dies by enabling the X processor cores on the first processor die, and enabling the remainder of cores, equal to Z?X, on the second processor die, based upon the determination that the second processor die is coupled to no I/O device.

Abstract: A security module authentication system includes a processing system that is configured to authenticate a security module based on a processing system type of the processing system. The system also includes a Basic Input/Output System (BIOS) coupled to the processing system and that includes a BIOS storage device. The BIOS storage stores a plurality of security modules each of which corresponds to a different processing system type. The BIOS is configured to utilize any of the plurality of security modules to perform a secure boot. The BIOS storage also stores an image table that identifies a first location in the BIOS storage of a first security module of the plurality of security modules. The first security module is authenticable by the processing system based on the processing system type of the processing system.

Abstract: A security module authentication system includes a processing system that is configured to authenticate a security module based on a processing system type of the processing system. The system also includes a Basic Input/Output System (BIOS) coupled to the processing system and that includes a BIOS storage device. The BIOS storage stores a plurality of security modules each of which corresponds to a different processing system type. The BIOS is configured to utilize any of the plurality of security modules to perform a secure boot. The BIOS storage also stores an image table that identifies a first location in the BIOS storage of a first security module of the plurality of security modules. The first security module is authenticable by the processing system based on the processing system type of the processing system.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor, a memory communicatively coupled to the processor and comprising a plurality of non-volatile memories, and a failure analysis module comprising a program of instructions, the failure analysis module configured to, when read and executed by the processor, set a predictive failure threshold for each of the plurality of non-volatile memories based at least on functional parameters of such non-volatile memory, and adapt the predictive failure threshold for each of the plurality of non-volatile memories based at least on health status parameters of such non-volatile memory.

Abstract: An information handling system may include a non-volatile memory and a processor system coupled to the non-volatile memory to access the non-volatile memory. The processor system may include a processor core and a corresponding platform security processor (PSP) having PSP memory. A BIOS of the processor system running on the processor core may store data at locations in the non-volatile memory and provide these memory locations to the PSP. The PSP stores these non-volatile memory locations in PSP memory and maintains the data in the non-volatile memory at the locations during an event affecting the processor system.

Abstract: A method, information handling system (IHS) and sub-system for enabling booting of the IHS using different operating system configurations. The method includes retrieving, via a processor, a unified extensible firmware interface (UEFI) image from a storage device and initializing at least one UEFI runtime service. The processor determines if a memory map corresponding to the UEFI runtime service defines multiple memory descriptors. In response to determining that the memory map defines multiple memory descriptors, a common memory descriptor is identified. The UEFI runtime service and the corresponding memory map are aligned to the common memory descriptor. The aligned UEFI runtime service and the corresponding memory map are copied to a system memory of the IHS. The operating system is booted, wherein the aligned UEFI runtime service and the corresponding memory map are compatible with operating systems that support single runtime memory descriptors.

Abstract: A memory device update system includes a computing device couple to a management device. While the computing device is in a pre-boot environment, a memory device update engine in the computing device assigns a memory type, which is associated with the storage of memory device update information, to memory region(s) in a memory subsystem in the computing device. Subsequent to a boot of the computing device such that the computing device is in a runtime environment, the memory device update engine retrieves memory device update information from the management device and uses a data communication interface between the memory device update engine and the memory subsystem to write the memory device update information to the memory region(s) that were assigned the memory type. While the computing device is in the runtime environment, the memory subsystem then uses the memory device update information to update the memory subsystem.

Abstract: An information handling system includes an I/O device, a first processor die coupled to the I/O device, a second processor die coupled to the first processor die, and to no I/O device, and boot process logic. The boot process logic determines that the first processor die is coupled to the I/O device and that the second processor die is coupled to no I/O device, determines that an operating environment of the information handling system is capable of utilizing a maximum of Z processor cores, where Z is an integer number that is greater than X and less than the sum of X+Y, and enables Z processor cores on the first and second processor dies by enabling the X processor cores on the first processor die, and enabling the remainder of cores, equal to Z?X, on the second processor die, based upon the determination that the second processor die is coupled to no I/O device.

Abstract: An information handling system may include a non-volatile memory and a processor system coupled to the non-volatile memory to access the non-volatile memory. The processor system may include a processor core and a corresponding platform security processor (PSP) having PSP memory. A BIOS of the processor system running on the processor core may store data at locations in the non-volatile memory and provide these memory locations to the PSP. The PSP stores these non-volatile memory locations in PSP memory and maintains the data in the non-volatile memory at the locations during an event affecting the processor system.

Abstract: An information handling system for enhanced system management mode (SMM) security may include a processor, system management random access memory (SMRAM), persistent memory, and basic input/output (BIOS) memory. The system may include instructions that, when loaded and executed by the processor, cause the processor to initialize the memory, initialize the BIOS memory, initialize the persistent memory, and check whether the system has previously executed a power-on self test (POST) routine. Based on a determination that the system has not previously executed a POST routine, the processor may unzip the SMM Code located in the BIOS memory store the unzipped SMM Code in the persistent memory and in the SMRAM. Based on a determination that the system has previously executed a POST routine, the processor may create a duplicate copy of the SMM Code from the persistent memory and store the duplicate copy in the SMRAM.

Abstract: A method, information handling system (IHS) and sub-system for enabling booting of the IHS using different operating system configurations. The method includes retrieving, via a processor, a unified extensible firmware interface (UEFI) image from a storage device and initializing at least one UEFI runtime service. The processor determines if a memory map corresponding to the UEFI runtime service defines multiple memory descriptors. In response to determining that the memory map defines multiple memory descriptors, a common memory descriptor is identified. The UEFI runtime service and the corresponding memory map are aligned to the common memory descriptor. The aligned UEFI runtime service and the corresponding memory map are copied to a system memory of the IHS. The operating system is booted, wherein the aligned UEFI runtime service and the corresponding memory map are compatible with operating systems that support single runtime memory descriptors.

Abstract: An information handling system for enhanced system management mode (SMM) security may include a processor, system management random access memory (SMRAM), persistent memory, and basic input/output (BIOS) memory. The system may include instructions that, when loaded and executed by the processor, cause the processor to initialize the memory, initialize the BIOS memory, initialize the persistent memory, and check whether the system has previously executed a power-on self test (POST) routine. Based on a determination that the system has not previously executed a POST routine, the processor may unzip the SMM Code located in the BIOS memory store the unzipped SMM Code in the persistent memory and in the SMRAM. Based on a determination that the system has previously executed a POST routine, the processor may create a duplicate copy of the SMM Code from the persistent memory and store the duplicate copy in the SMRAM.