Patents by Inventor Vijay Bharat Nijhawan

Vijay Bharat Nijhawan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10303487
    Abstract: A method, information handling system (IHS) and sub-system for enabling booting of the IHS using different operating system configurations. The method includes retrieving, via a processor, a unified extensible firmware interface (UEFI) image from a storage device and initializing at least one UEFI runtime service. The processor determines if a memory map corresponding to the UEFI runtime service defines multiple memory descriptors. In response to determining that the memory map defines multiple memory descriptors, a common memory descriptor is identified. The UEFI runtime service and the corresponding memory map are aligned to the common memory descriptor. The aligned UEFI runtime service and the corresponding memory map are copied to a system memory of the IHS. The operating system is booted, wherein the aligned UEFI runtime service and the corresponding memory map are compatible with operating systems that support single runtime memory descriptors.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: May 28, 2019
    Assignee: Dell Products, L.P.
    Inventors: Sumanth Vidyadhara, Parmeshwr Prasad, Vijay Bharat Nijhawan
  • Patent number: 10152264
    Abstract: A memory device update system includes a computing device couple to a management device. While the computing device is in a pre-boot environment, a memory device update engine in the computing device assigns a memory type, which is associated with the storage of memory device update information, to memory region(s) in a memory subsystem in the computing device. Subsequent to a boot of the computing device such that the computing device is in a runtime environment, the memory device update engine retrieves memory device update information from the management device and uses a data communication interface between the memory device update engine and the memory subsystem to write the memory device update information to the memory region(s) that were assigned the memory type. While the computing device is in the runtime environment, the memory subsystem then uses the memory device update information to update the memory subsystem.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: December 11, 2018
    Assignee: Dell Products L.P.
    Inventors: Wade Andrew Butcher, Vijay Bharat Nijhawan, Vadhiraj Sankaranarayanan
  • Publication number: 20180341614
    Abstract: An information handling system includes an I/O device, a first processor die coupled to the I/O device, a second processor die coupled to the first processor die, and to no I/O device, and boot process logic. The boot process logic determines that the first processor die is coupled to the I/O device and that the second processor die is coupled to no I/O device, determines that an operating environment of the information handling system is capable of utilizing a maximum of Z processor cores, where Z is an integer number that is greater than X and less than the sum of X+Y, and enables Z processor cores on the first and second processor dies by enabling the X processor cores on the first processor die, and enabling the remainder of cores, equal to Z?X, on the second processor die, based upon the determination that the second processor die is coupled to no I/O device.
    Type: Application
    Filed: May 26, 2017
    Publication date: November 29, 2018
    Inventors: Mukund P. Khatri, Vijay Bharat Nijhawan
  • Publication number: 20180300485
    Abstract: An information handling system may include a non-volatile memory and a processor system coupled to the non-volatile memory to access the non-volatile memory. The processor system may include a processor core and a corresponding platform security processor (PSP) having PSP memory. A BIOS of the processor system running on the processor core may store data at locations in the non-volatile memory and provide these memory locations to the PSP. The PSP stores these non-volatile memory locations in PSP memory and maintains the data in the non-volatile memory at the locations during an event affecting the processor system.
    Type: Application
    Filed: April 18, 2017
    Publication date: October 18, 2018
    Inventors: Anh Luong, Vijay Bharat Nijhawan
  • Patent number: 10101928
    Abstract: An information handling system for enhanced system management mode (SMM) security may include a processor, system management random access memory (SMRAM), persistent memory, and basic input/output (BIOS) memory. The system may include instructions that, when loaded and executed by the processor, cause the processor to initialize the memory, initialize the BIOS memory, initialize the persistent memory, and check whether the system has previously executed a power-on self test (POST) routine. Based on a determination that the system has not previously executed a POST routine, the processor may unzip the SMM Code located in the BIOS memory store the unzipped SMM Code in the persistent memory and in the SMRAM. Based on a determination that the system has previously executed a POST routine, the processor may create a duplicate copy of the SMM Code from the persistent memory and store the duplicate copy in the SMRAM.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: October 16, 2018
    Assignee: Dell Products L.P.
    Inventors: Vijay Bharat Nijhawan, Sumanth Vidyadhara
  • Publication number: 20170337064
    Abstract: A method, information handling system (IHS) and sub-system for enabling booting of the IHS using different operating system configurations. The method includes retrieving, via a processor, a unified extensible firmware interface (UEFI) image from a storage device and initializing at least one UEFI runtime service. The processor determines if a memory map corresponding to the UEFI runtime service defines multiple memory descriptors. In response to determining that the memory map defines multiple memory descriptors, a common memory descriptor is identified. The UEFI runtime service and the corresponding memory map are aligned to the common memory descriptor. The aligned UEFI runtime service and the corresponding memory map are copied to a system memory of the IHS. The operating system is booted, wherein the aligned UEFI runtime service and the corresponding memory map are compatible with operating systems that support single runtime memory descriptors.
    Type: Application
    Filed: May 18, 2016
    Publication date: November 23, 2017
    Inventors: SUMANTH VIDYADHARA, PARMESHWR PRASAD, VIJAY BHARAT NIJHAWAN
  • Publication number: 20170242598
    Abstract: An information handling system for enhanced system management mode (SMM) security may include a processor, system management random access memory (SMRAM), persistent memory, and basic input/output (BIOS) memory. The system may include instructions that, when loaded and executed by the processor, cause the processor to initialize the memory, initialize the BIOS memory, initialize the persistent memory, and check whether the system has previously executed a power-on self test (POST) routine. Based on a determination that the system has not previously executed a POST routine, the processor may unzip the SMM Code located in the BIOS memory store the unzipped SMM Code in the persistent memory and in the SMRAM. Based on a determination that the system has previously executed a POST routine, the processor may create a duplicate copy of the SMM Code from the persistent memory and store the duplicate copy in the SMRAM.
    Type: Application
    Filed: February 19, 2016
    Publication date: August 24, 2017
    Inventors: Vijay Bharat Nijhawan, Sumanth Vidyadhara
  • Patent number: 6185677
    Abstract: A method and article of manufacture for the automatic generation of Advanced Configuration and Power Management Interface (“ACPI”) Source Language (“ASL”) code in a Basic Input-Output System (“BIOS”) of a computer system having an ACPI compliant BIOS. The method scans all device node structures in the BIOS to find the device node structures corresponding to static and MCD devices. ASL code is generated corresponding to the device node structure by extracting the PnP Id of the devices and generating the required control methods.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: February 6, 2001
    Assignee: Phoenix Technologies Ltd.
    Inventor: Vijay Bharat Nijhawan