Patents by Inventor Vijay Janapa Reddi

Vijay Janapa Reddi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for power reduction during lane divergence
    Patent number: 9690350
    Abstract: A method and device for reducing power during an instruction lane divergence includes idling an inactive execution lane during the lane divergence.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: June 27, 2017
    Assignee: Advances Micro Devices, Inc.
    Inventors: Nam Sung Kim, James M. O'Connor, Michael J. Schulte, Vijay Janapa Reddi
  • Adaptive event-guided system and method for avoiding voltage emergencies
    Patent number: 8949666
    Abstract: In a preferred embodiment, the present invention is a system for avoiding voltage emergencies. The system comprises a microprocessor, an actuator for throttling the microprocessor, a voltage emergency detector and a voltage emergency predictor. The voltage emergency detector may comprise, for example, a checkpoint recovery mechanism or a sensor. The voltage emergency predictor of a preferred embodiment comprises means for tracking control flow instructions and microarchitectural events, means for storing voltage emergency signatures that cause voltage emergencies, means for comparing current control flow and microarchitectural events with stored voltage emergency signatures to predict voltage emergencies, and means for actuating said actuator to throttle said microprocessor to avoid predicted voltage emergencies.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: February 3, 2015
    Assignee: President and Fellows of Harvard College
    Inventors: Vijay Janapa Reddi, Meeta Sharma Gupta, Glenn Holloway, Gu-Yeon Wei, Michael D. Smith, David Brooks
  • METHOD AND APPARATUS FOR POWER REDUCTION DURING LANE DIVERGENCE
    Publication number: 20140068304
    Abstract: A method and device for reducing power during an instruction lane divergence includes idling an inactive execution lane during the lane divergence.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 6, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Nam Sung Kim, James M. O'Connor, Michael J. Schulte, Vijay Janapa Reddi
  • ADAPTIVE EVENT-GUIDED SYSTEM AND METHOD FOR AVOIDING VOLTAGE EMERGENCIES
    Publication number: 20120005515
    Abstract: In a preferred embodiment, the present invention is a system for avoiding voltage emergencies. The system comprises a microprocessor, an actuator for throttling the microprocessor, a voltage emergency detector and a voltage emergency predictor. The voltage emergency detector may comprise, for example, a checkpoint recovery mechanism or a sensor. The voltage emergency predictor of a preferred embodiment comprises means for tracking control flow instructions and microarchitectural events, means for storing voltage emergency signatures that cause voltage emergencies, means for comparing current control flow and microarchitectural events with stored voltage emergency signatures to predict voltage emergencies, and means for actuating said actuator to throttle said microprocessor to avoid predicted voltage emergencies.
    Type: Application
    Filed: February 11, 2010
    Publication date: January 5, 2012
    Inventors: Vijay Janapa Reddi, Meeta Sharma Gupta, Glenn Holloway, Gu-Yeon Wei, Michael D. Smith, David Brooks