Patents by Inventor Vijay K. Vuppaladadium

Vijay K. Vuppaladadium has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11327523
    Abstract: A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Eyal Fayneh, Elias Nassar, Inbar Falkov, Ramkumar Krithivasan, Vijay K. Vuppaladadium, Miguel A. Corvacho Hernandez, Samer Nassar, Yair Talker
  • Publication number: 20200301465
    Abstract: A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.
    Type: Application
    Filed: February 24, 2020
    Publication date: September 24, 2020
    Applicant: Intel Corporation
    Inventors: Eyal FAYNEH, Elias NASSAR, Inbar FALKOV, Ramkumar KRITHIVASAN, Vijay K. VUPPALADADIUM, Miguel A. CORVACHO HERNANDEZ, Samer NASSAR, Yair TALKER
  • Patent number: 10571953
    Abstract: A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: Eyal Fayneh, Elias Nassar, Inbar Falkov, Ramkumar Krithivasan, Vijay K. Vuppaladadium, Miguel A. Corvacho Hernandez, Samer Nasser, Yair Talker
  • Publication number: 20190011945
    Abstract: A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.
    Type: Application
    Filed: July 5, 2017
    Publication date: January 10, 2019
    Applicant: Intel Corporation
    Inventors: Eyal FAYNEH, Elias NASSAR, Inbar FALKOV, Ramkumar KRITHIVASAN, Vijay K. VUPPALADADIUM, Miguel A. CORVACHO HERNANDEZ, Samer NASSER, Yair TALKER
  • Patent number: 9223365
    Abstract: A system, semiconductor device and method for providing a controlled system reset sequence with lower power consumption without dependency on fuses, PLL's and external XTAL's. A method to simplify a boot sequence by using a ring oscillator that compensates for voltage and temperature variations while also removing the dependency on parallel fuses, PLL's and external XTAL's.
    Type: Grant
    Filed: March 16, 2013
    Date of Patent: December 29, 2015
    Assignee: Intel Corporation
    Inventors: Ivan Herrera Mejia, Vishram Sarurkar, Vijay K. Vuppaladadium
  • Publication number: 20140281641
    Abstract: A system, semiconductor device and method for providing a controlled system reset sequence with lower power consumption without dependency on fuses, PLL's and external XTAL's. A method to simplify a boot sequence by using a ring oscillator that compensates for voltage and temperature variations while also removing the dependency on parallel fuses, PLL's and external XTAL's.
    Type: Application
    Filed: March 16, 2013
    Publication date: September 18, 2014
    Applicant: Intel Corporation
    Inventors: Ivan Herrera Mejia, Vishram Sarurkar, Vijay K. Vuppaladadium
  • Patent number: 7496803
    Abstract: A plurality of timing diagrams and different versions of circuits to test an integrated device in a test mode of operation. The invention allows for pulling in a strobe and eliminating the need for delay cells in strobe pads and a clock generation that facilitates varying the duty cycle for pulling in the strobe and pushing out the data.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: February 24, 2009
    Assignee: Intel Corporation
    Inventors: Tanveer R. Khondker, Matthew B. Nazareth, Vijay K. Vuppaladadium