Patents by Inventor Vijay Karamcheti

Vijay Karamcheti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220035699
    Abstract: Systems and methods for increasing the endurance of a solid state drive are disclosed. The disclosed systems and methods can assign different levels of error protection to a plurality of blocks of the solid state drive. The disclosed methods can provide a plurality of error correction mechanisms, each having a plurality of corresponding error correction levels and associate a first plurality of blocks of the solid state drive with a first zone and a second plurality of blocks of the solid state drive with a second zone. The disclosed methods can assign a first error correction mechanism and a first corresponding error correction level to the first zone and can assign a second error correction mechanism and a second corresponding error correction level to the second zone.
    Type: Application
    Filed: October 14, 2021
    Publication date: February 3, 2022
    Inventors: Ashish SINGHAI, Vijay KARAMCHETI, Ashwin NARASIMHA
  • Patent number: 11182252
    Abstract: Embodiments of the present invention provide systems and methods for recovering a high availability storage system. The storage system includes a first layer and a second layer, each layer including a controller board, a router board, and storage elements. When a component of a layer fails, the storage system continues to function in the presence of a single failure of any component, up to two storage element failures in either layer, or a single power supply failure. While a component is down, the storage system will run in a degraded mode. The passive zone is not serving input/output requests, but is continuously updating its state in dynamic random access memory to enable failover within a short period of time using the layer that is fully operational. When the issue with the failed zone is corrected, a failback procedure brings the system back to a normal operating state.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: November 23, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ladislav Steffko, Vijay Karamcheti
  • Patent number: 11150984
    Abstract: Systems and methods for increasing the endurance of a solid state drive are disclosed. The disclosed systems and methods can assign different levels of error protection to a plurality of blocks of the solid state drive. The disclosed methods can provide a plurality of error correction mechanisms, each having a plurality of corresponding error correction levels and associate a first plurality of blocks of the solid state drive with a first zone and a second plurality of blocks of the solid state drive with a second zone. The disclosed methods can assign a first error correction mechanism and a first corresponding error correction level to the first zone and can assign a second error correction mechanism and a second corresponding error correction level to the second zone.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: October 19, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ashish Singhai, Vijay Karamcheti, Ashwin Narasimha
  • Publication number: 20200218603
    Abstract: Systems and methods for increasing the endurance of a solid state drive are disclosed. The disclosed systems and methods can assign different levels of error protection to a plurality of blocks of the solid state drive. The disclosed methods can provide a plurality of error correction mechanisms, each having a plurality of corresponding error correction levels and associate a first plurality of blocks of the solid state drive with a first zone and a second plurality of blocks of the solid state drive with a second zone. The disclosed methods can assign a first error correction mechanism and a first corresponding error correction level to the first zone and can assign a second error correction mechanism and a second corresponding error correction level to the second zone.
    Type: Application
    Filed: March 19, 2020
    Publication date: July 9, 2020
    Inventors: Ashish SINGHAI, Vijay KARAMCHETI, Ashwin NARASIMHA
  • Patent number: 10691531
    Abstract: Systems and methods for increasing the endurance of a solid state drive are disclosed. The disclosed systems and methods can assign different levels of error protection to a plurality of blocks of the solid state drive. The disclosed methods can provide a plurality of error correction mechanisms, each having a plurality of corresponding error correction levels and associate a first plurality of blocks of the solid state drive with a first zone and a second plurality of blocks of the solid state drive with a second zone. The disclosed methods can assign a first error correction mechanism and a first corresponding error correction level to the first zone and can assign a second error correction mechanism and a second corresponding error correction level to the second zone.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: June 23, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ashish Singhai, Vijay Karamcheti, Ashwin Narasimha
  • Patent number: 10565057
    Abstract: A data storage system comprises, a storage device having segments that are configured to store data, and storage logic coupled to the storage device that manages storage of data on the storage device using a translation table. The storage logic is executable to receive a first marker as part of a backup request, generate a second marker encapsulating a state of the storage device at a second time, calculate a difference between the first marker and the second marker, and generate a backup of data stored in the storage device based on the calculated difference between the first marker and the second marker. A garbage collection (GC) barrier may be set based on serial numbers associated with backup segments, and the garbage collection barrier may be incrementally released by releasing the garbage collection barrier for each segment after the segment has been backed up.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: February 18, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ashish Singhai, Vijay Karamcheti, Ashwin Narasimha
  • Patent number: 10474397
    Abstract: The disclosed multi-device platform includes, by way of example, a system that receives a host command including a logical address and determines a hybrid storage device unit based on the logical address. The hybrid storage device unit has a set of hybrid physical storage devices and the set of hybrid physical storage devices includes one or more magnetic storage devices and one or more flash storage devices. The system selects a first plurality of physical storage devices from the set of hybrid physical storage devices, generates a plurality of device commands for the first plurality of physical storage devices based on the host command, and executes the plurality of device commands on the first plurality of physical storage devices.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: November 12, 2019
    Assignee: Western Digital Technologies, Inc
    Inventors: Bernd Lamberts, Vijay Karamcheti
  • Patent number: 10467100
    Abstract: Embodiments of the present invention provide systems and methods for recovering a high availability storage system. The storage system includes a first layer and a second layer, each layer including a controller board, a router board, and storage elements. When a component of a layer fails, the storage system continues to function in the presence of a single failure of any component, up to two storage element failures in either layer, or a single power supply failure. While a component is down, the storage system will run in a degraded mode. The passive zone is not serving input/output requests, but is continuously updating its state in dynamic random access memory to enable failover within a short period of time using the layer that is fully operational. When the issue with the failed zone is corrected, a failback procedure brings the system back to a normal operating state.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: November 5, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ladislav Steffko, Vijay Karamcheti
  • Publication number: 20190317861
    Abstract: Embodiments of the present invention provide systems and methods for recovering a high availability storage system. The storage system includes a first layer and a second layer, each layer including a controller board, a router board, and storage elements. When a component of a layer fails, the storage system continues to function in the presence of a single failure of any component, up to two storage element failures in either layer, or a single power supply failure. While a component is down, the storage system will run in a degraded mode. The passive zone is not serving input/output requests, but is continuously updating its state in dynamic random access memory to enable failover within a short period of time using the layer that is fully operational. When the issue with the failed zone is corrected, a failback procedure brings the system back to a normal operating state.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Inventors: Ladislav STEFFKO, Vijay KARAMCHETI
  • Patent number: 10353813
    Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to determine a first value of a first checkpoint associated with a first snapshot, receive a second value of a second checkpoint associated with a translation table entry from an additional source, determine whether the second value of the second checkpoint is after the first value of the first checkpoint, in response to determining that the second value of the second checkpoint is after the first value of the first checkpoint, retrieve the translation table entry associated with the second checkpoint from the additional source, and reconstruct the translation table using the translation table entry associated with the second checkpoint.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: July 16, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ajith Kumar Battaje, Tanay Goel, Sandeep Sharma, Saurabh Manchanda, Ashish Singhai, Vijay Karamcheti
  • Patent number: 10275376
    Abstract: A method for implementing cross device redundancy schemes with a single commit by receiving, by a write page allocation unit, a request to allocate data grains; responsive to receiving the request, performing, by the write page allocation unit, an analysis of a predetermined data layout map associated with a grain memory to identify a memory segment; allocating, by the write page allocation unit, a number of data grains to the memory segment, while computing redundancy data associated with the number of data grains; storing the number of data grains and the redundancy data to the memory segment of the grain memory; determining, by the write page allocation unit, whether a storage threshold associated with the grain memory has been satisfied; and responsive to the storage threshold associated with the grain memory being satisfied, transmitting data grains and redundancy data stored in the memory segment to one or more storage devices.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: April 30, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ashwin Narasimha, Krishanth Skandakumaran, Vijay Karamcheti, Ashish Singhai
  • Patent number: 10191842
    Abstract: An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: January 29, 2019
    Assignee: VIRIDENT SYSTEMS, LLC
    Inventors: Vijay Karamcheti, Kumar Ganapathy, Kenneth Alan Okin, Rajesh Parekh
  • Patent number: 10156890
    Abstract: In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: December 18, 2018
    Assignee: VIRIDENT SYSTEMS, LLC
    Inventors: Vijay Karamcheti, Kenneth Alan Okin, Kumar Ganapathy
  • Publication number: 20180356992
    Abstract: The disclosed multi-device platform includes, by way of example, a system that receives a host command including a logical address and determines a hybrid storage device unit based on the logical address. The hybrid storage device unit has a set of hybrid physical storage devices and the set of hybrid physical storage devices includes one or more magnetic storage devices and one or more flash storage devices. The system selects a first plurality of physical storage devices from the set of hybrid physical storage devices, generates a plurality of device commands for the first plurality of physical storage devices based on the host command, and executes the plurality of device commands on the first plurality of physical storage devices.
    Type: Application
    Filed: June 13, 2017
    Publication date: December 13, 2018
    Inventors: Bernd Lamberts, Vijay Karamcheti
  • Patent number: 10152389
    Abstract: An apparatus for inline compression and deduplication includes a memory unit and a processor coupled to the memory unit. The processor is configured to receive a subset of data from a data stream and select a reference data block corresponding to the subset of data, in which the reference data block is stored in a memory buffer resident in the memory unit. The processor is also configured to compare a first hash value computed for the subset of data to a second hash value computed for the reference data block, in which the first hash value and the second hash value are stored in separate hash tables and generate a compressed representation of the subset of data by modifying header data corresponding to the subset of data responsive to a detected match between the first hash value and the second hash value in one of the separate hash tables.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: December 11, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ashwin Narasimha, Ashish Singhai, Vijay Karamcheti
  • Patent number: 10089360
    Abstract: Embodiments of the present invention include a memory unit and a processor coupled to a memory unit. The processor is operable to group a plurality of subsets of data from an input data stream and compute a first hash value corresponding to a first grouped subset of data. Additionally, the processor is operable to detect a match between the first hash value and a second hash value stored in a hash table. Furthermore, the processor is also configured to monitor a hash value match frequency for the input data stream in which the processor is operable to increment a counter value responsive to a detection of the match and determine an entropy level for the input data stream based on the counter value relative to a frequent hash value match threshold.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: October 2, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ashwin Narasimha, Ashish Singhai, Vijay Karamcheti, Krishanth Skandakumaran
  • Patent number: 10082957
    Abstract: A storage cartridge may include a storage controller comprising a single PCIe port and a PCIe switch. The PCIe switch may include a first PCIe port communicatively coupled to a first PCIe fabric, a second PCIe port communicatively coupled to a second, different PCIe fabric, and a third PCIe port communicatively coupled to the single PCIe port of the storage controller. The first PCIe port and the second PCIe port may be configured to be selectively communicatively coupled to a non-transparent bridge (NTB) of the PCIe switch.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: September 25, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Pinchas Herman, Vijay Karamcheti, Rodney N. Mullendore, William H. Radke
  • Patent number: 10073626
    Abstract: Some implementations include a method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem that includes NVRAM devices. The method includes: receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem; categorizing the write requests into subgroups of write requests, where write requests within respective subgroups are mutually exclusive; ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem; identifying a target location on at least one NVRAM device to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem; and servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 11, 2018
    Assignee: VIRIDENT SYSTEMS, LLC
    Inventors: Vijay Karamcheti, Ashish Singhai, Shibabrata Mondal, Ajith Kumar
  • Patent number: 10049055
    Abstract: Some implementations provide a method for managing data in a storage system that includes a persistent storage device and a non-volatile random access memory (NVRAM) cache device. The method includes: accessing a direct mapping between a logical address associated with data stored on the persistent storage device and a physical address on the NVRAM cache device; receiving, from a host computing device coupled to the storage system, a request to access a particular unit of data stored on the persistent storage device; using the direct mapping as a basis between the logical address associated with the data stored on the persistent storage device and the physical address on the NVRAM cache device to determine whether the particular unit of data being requested is present on the NVRAM cache device.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: August 14, 2018
    Assignee: VIRIDIENT SYSTEMS, INC
    Inventors: Shibabrata Mondal, Vijay Karamcheti, Ankur Arora, Ajit Yagaty
  • Patent number: 9983797
    Abstract: In one embodiment of the invention, a server is disclosed including a main printed circuit board; a plurality of processors mounted to the main printed circuit board; and a memory system accessible to the plurality of processors. The memory system includes a plurality of expansion sockets mounted to the printed circuit board, and a plurality of server memory cards removeably plugged into the plurality of expansion sockets. Each server memory card includes a master controller, a plurality of slave controllers, and a plurality of replaceable daughter-memory-cards with read-writeable non-volatile memory.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: May 29, 2018
    Assignee: VIRIDENT SYSTEMS, LLC
    Inventors: Vijay Karamcheti, Shibabrata Mondal, Ajith Kumar