Abstract: A simulator can simulate a circuit design describing an electronic device using a single processing device of a computing system. The simulator can generate profile data associated with compilation of the circuit design and the single processing device simulation of the compiled circuit design. The profile data can identify multiple different ways to partition the circuit design and include information corresponding to the single processing device simulation of the compiled circuit design. A parallel simulation qualifier can determine a parallelism factor corresponding to an expected performance of the computing system in a multiple processing device simulation of the circuit design based on the profile data from the single processing device simulation of the circuit design. The simulator can utilize the parallelism factor to partition the circuit design in one of the different ways, and simulate the partitioned circuit design with multiple processing devices of the computing system.