Abstract: An input signal is filtered for creating an output signal using an adaptive filter. An error signal is derived from the output signal. The adaptive filter has coefficient whose value can be modified. A value of a coefficient is modified using a derived updating amount. The updating amount is obtained from the product of a value of the input signal, a value of the polarity of the error signal, and a step gain. The step gain has the form 2K with K being an integer and being dependent on a magnitude of the value of the error signal and on a step gain parameter. The updating amount is dependent on both the magnitude and the polarity of the error signal, therefore allowing a precise update of the coefficient. The specific form of the step gain allows a fast derivation of the product.

Abstract: An address generator for a pixel shuffler used in a relective liquid crystal display (RLCD) digital video system, and a pixel shuffler incorporating such an address generator. The address generator includes a small, dual port SRAM 160×8, a combinatorial converter having a pair of inputs and an output representing a predetermined relationship of the inputs, a pixel counter with a pair of decoders, a line counter, a computing block for selectively implementing a mirror reflection of the pixel addresses, as well as a plurality of D flip flops and logic elements. The pixel shuffler operates in read-modify-write mode, whereby any address location of memory is read and immediately overwritten with the new data. This permits operation with only one bank of SRAM 320×96 rather than the customary two banks for prior art pixel shufflers using the so-called Ping Pong method.

Abstract: An address generator for a pixel shuffler used in a relective liquid crystal display (RLCD) digital video system, and a pixel shuffler incorporating such an address generator. The address generator includes a small, dual port SRAM 160×8, a combinatorial converter having a pair of inputs and an output representing a predetermined relationship of the inputs, a pixel counter with a pair of decoders, a line counter, a computing block for selectively implementing a mirror reflection of the pixel addresses, as well as a plurality of D flip flops and logic elements. The pixel shuffler operates in read-modify-write mode, whereby any address location of memory is read and immediately overwritten with the new data. This permits operation with only one bank of SRAM 320×96 rather than the customary two banks for prior art pixel shufflers using the so-called Ping Pong method.

Abstract: A RAM-based search engine for updating a horizontal sum representing the sum of the values of N pixels contained in a horizontal row of a reference pixel array during a motion estimation search during which the reference pixel array is displaced by one pixel in a horizontal search direction during each of a plurality of iterations of the motion estimation search.

Abstract: A one-hot overflow matrix which includes a first one-hot input comprised of a plurality n of parallel bits arranged in sequence from a zero bit position to an (n-1) bit position, a second one-hot input comprised of a plurality n of parallel bits arranged in sequence from a zero bit position to an (n-1) bit position, a plurality n of output gates (e.g., tri-state buffers) each having a first input, a second input, and an output, a data output line commonly coupled to the output of each of the output gates, a plurality n/2 of NOR gates each having one or more data inputs, and a data output, and a plurality (n/2-1) of OR gates each having one or more data inputs, and a data output. The data input(s) of each respective ith one of the NOR gates are respectively coupled to the zero bit position through ((n-1)-i) bit position bit(s) of the second one-hot input.

Abstract: An apparatus for automatically synchronizing a video system to one of a plurality of composite synchronizing signals in accordance with a plurality of known video formats, includes a number of synchronizing signal stripper circuits, corresponding, respectively, to a number of types of composite synchronizing signals, a horizontal analyzer, having a plurality of horizontal standard identification circuits corresponding to a identification circuits for each known horizontal synchronizing signal rate for each type of composite synchronizing signal, for determining an approximate horizontal synchronizing signal rate and, a vertical analyzer, having a plurality of vertical rate identification circuits corresponding to the number of different known vertical rates, for determining the vertical synchronizing signal rate.

Abstract: A high speed variable length decoder with an enhanced architecture for minimizing the propagation delays within the processing paths of the variable length decoder. The variable length decoder includes an input circuit for receiving code words and outputting a sequence of bits on a corresponding sequence of parallel lines that define a decoding window. The input circuit preferably includes a "one-hot" bit stream barrel shifter matrix having a shift input. The decoding window is input to a "one-hot" word length decoder that provides a numbered sequence of output lines. The "one-hot" word length output of the "one-hot" word length decoder is applied to an input of a "one-hot" ring barrel shifter matrix, and an input of a "one-hot" overflow barrel shifter matrix. The output of the "one-hot" ring barrel shifter matrix is a "one-hot" word pointer which shifts the decoding window to the next code word to be decoded.

Abstract: A transformerless high-voltage generator circuit includes an amplifier and a feedback circuit connected together to form an oscillator. Due to the configuration of the feedback circuit, a high-voltage output is obtained at an intermediate point within the feedback circuit without the use of a transformer. The resulting circuit may be used in various applications, such as an electronic photoflash unit, in order to reduce the size, weight and cost of the finished product by eliminating the need for a transformer to obtain the desired high voltage.

Abstract: An apparatus, such as an adaptive flywheel, and method for producing periodic time references, forming a periodic time reference signal, from uncertain time references. A counter counts from a first count value to a second count value and provides a periodic time reference each time its count reaches the second count value. An error processing device, coupled to the counter, determines (a) whether an uncertain time reference is received within a predetermined range of count values (corresponding to a window of expectation), or (b) whether the absolute value of the average of an error, corresponding to the number of increment values before or after the second count value, whichever is lower, the count is at when an uncertain synchronization reference is received, and at least one previously determined error for at least one previously received uncertain synchronization reference is greater than WC/2 increment values.