Patents by Inventor Vilas K. Sridharan

Vilas K. Sridharan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220197827
    Abstract: A method and system for memory attack mitigation in a memory device includes receiving, at a memory controller, an allocation of a page in memory. One or more device controllers detects an aggressor-victim set within the memory. Based upon the detection, an address of the allocated page is identified for further action.
    Type: Application
    Filed: December 17, 2020
    Publication date: June 23, 2022
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Sudhanva Gurumurthi, Vilas K. Sridharan
  • Publication number: 20210342241
    Abstract: A method and apparatus for predicting and managing a device failure includes responsive to a predicted failure of a memory device, the predicted failure based on sensor data associated with the memory device, determining a further action for the memory device.
    Type: Application
    Filed: April 29, 2020
    Publication date: November 4, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Sudhanva Gurumurthi, Vilas K. Sridharan
  • Patent number: 11061753
    Abstract: Systems, apparatuses, and methods for implementing a hardware enforcement mechanism to enable platform-specific firmware visibility into an error state ahead of the operating system are disclosed. A system includes at least one or more processor cores, control logic, a plurality of registers, platform-specific firmware, and an operating system (OS). The control logic allows the platform-specific firmware to decide if and when the error state is visible to the OS. In some cases, the platform-specific firmware blocks the OS from accessing the error state. In other cases, the platform-specific firmware allows the OS to access the error state such as when the OS needs to unmap a page. The control logic enables the platform-specific firmware, rather than the OS, to make decisions about the replacement of faulty components in the system.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: July 13, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dean A. Liberty, Vilas K. Sridharan, Michael T. Clark, Jelena Ilic, David S. Christie, James R. Williamson, Cristian Constantinescu
  • Publication number: 20210182135
    Abstract: A method and apparatus for predicting and managing a fault in memory includes detecting an error in data. The error is compared to one or more stored errors in a filter, and based upon the comparison, the error is predicted as a transient error or a permanent error for further action.
    Type: Application
    Filed: December 17, 2019
    Publication date: June 17, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Sudhanva Gurumurthi, Vilas K. Sridharan
  • Publication number: 20190303230
    Abstract: Systems, apparatuses, and methods for implementing a hardware enforcement mechanism to enable platform-specific firmware visibility into an error state ahead of the operating system are disclosed. A system includes at least one or more processor cores, control logic, a plurality of registers, platform-specific firmware, and an operating system (OS). The control logic allows the platform-specific firmware to decide if and when the error state is visible to the OS. In some cases, the platform-specific firmware blocks the OS from accessing the error state. In other cases, the platform-specific firmware allows the OS to access the error state such as when the OS needs to unmap a page. The control logic enables the platform-specific firmware, rather than the OS, to make decisions about the replacement of faulty components in the system.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Inventors: Dean A. Liberty, Vilas K. Sridharan, Michael T. Clark, Jelena Ilic, David S. Christie, James R. Williamson, Cristian Constantinescu
  • Patent number: 9734059
    Abstract: A method of way prediction for a data cache having a plurality of ways is provided. Responsive to an instruction to access a stack data block, the method accesses identifying information associated with a plurality of most recently accessed ways of a data cache to determine whether the stack data block resides in one of the plurality of most recently accessed ways of the data cache, wherein the identifying information is accessed from a subset of an array of identifying information corresponding to the plurality of most recently accessed ways; and when the stack data block resides in one of the plurality of most recently accessed ways of the data cache, the method accesses the stack data block from the data cache.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: August 15, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lena E. Olson, Yasuko Eckert, Vilas K. Sridharan, James M. O'Connor, Mark D. Hill, Srilatha Manne
  • Patent number: 9354970
    Abstract: A method and device are described for encoding erroneous data in an error correction code (ECC) protected memory. In one embodiment, incoming data including a plurality of data symbols and a data integrity marker is received. At least one extra symbol is used to mark the incoming data as error-free data or erroneous data (i.e., poison) based on the data integrity marker. ECC may be created to protect the data symbols. The ECC may include a plurality of check symbols, a plurality of unused symbols and the at least one extra symbol. In another embodiment, an error marker may be propagated from a single ECC word to all ECC words of data block (e.g., a cache line, a page, and the like) to prevent errors due to corruption of the error marker caused by faulty memory in the erroneous ECC word.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: May 31, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ross V. La Fetra, Vilas K. Sridharan, Vydhyanathan Kalyanasundharam, Dean A. Liberty, Amit P. Apte
  • Patent number: 9298615
    Abstract: A method of partitioning a data cache comprising a plurality of sets, the plurality of sets comprising a plurality of ways, is provided. Responsive to a stack data request, the method stores a cache line associated with the stack data in one of a plurality of designated ways of the data cache, wherein the plurality of designated ways is configured to store all requested stack data.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: March 29, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lena E. Olson, Yasuko Eckert, Vilas K. Sridharan, James M. O'Connor, Mark D. Hill, Srilatha Manne
  • Patent number: 9229803
    Abstract: A method of managing memory includes installing a first cacheline at a first location in a cache memory and receiving a write request. In response to the write request, the first cacheline is modified in accordance with the write request and marked as dirty. Also in response to the write request, a second cacheline is installed that duplicates the first cacheline, as modified in accordance with the write request, at a second location in the cache memory.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: January 5, 2016
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Gabriel H. Loh, Vilas K. Sridharan, James M. O'Connor, Jaewoong Sim
  • Patent number: 9189326
    Abstract: Hard errors in the memory array can be detected and corrected in real-time using reusable entries in an error status buffer. Data may be rewritten to a portion of a memory array and a register in response to a first error in data read from the portion of the memory array. The rewritten data may then be written from the register to an entry of an error status buffer in response to the rewritten data read from the register differing from the rewritten data read from the portion of the memory array.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: November 17, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Johnsy Kanjirapallil John, Robert Gelinas, Vilas K. Sridharan, Phillip E. Nevius
  • Publication number: 20150293845
    Abstract: Described is a system and method for a multi-level memory hierarchy. Each level is based on different attributes including, for example, power, capacity, bandwidth, reliability, and volatility. In some embodiments, the different levels of the memory hierarchy may use an on-chip stacked dynamic random access memory, (providing fast, high-bandwidth, low-energy access to data) and an off-chip non-volatile random access memory, (providing low-power, high-capacity storage), in order to provide higher-capacity, lower power, and higher-bandwidth performance. The multi-level memory may present a unified interface to a processor so that specific memory hardware and software implementation details are hidden. The multi-level memory enables the illusion of a single-level memory that satisfies multiple conflicting constraints. A comparator receives a memory address from the processor, processes the address and reads from or writes to the appropriate memory level.
    Type: Application
    Filed: April 11, 2014
    Publication date: October 15, 2015
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Lisa R. Hsu, James M. O'Connor, Vilas K. Sridharan, Gabriel H. Loh, Nuwan S. Jayasena, Bradford M. Beckmann
  • Publication number: 20150278016
    Abstract: A method and device are described for encoding erroneous data in an error correction code (ECC) protected memory. In one embodiment, incoming data including a plurality of data symbols and a data integrity marker is received. At least one extra symbol is used to mark the incoming data as error-free data or erroneous data (i.e., poison) based on the data integrity marker. ECC may be created to protect the data symbols. The ECC may include a plurality of check symbols, a plurality of unused symbols and the at least one extra symbol. In another embodiment, an error marker may be propagated from a single ECC word to all ECC words of data block (e.g., a cache line, a page, and the like) to prevent errors due to corruption of the error marker caused by faulty memory in the erroneous ECC word.
    Type: Application
    Filed: March 31, 2014
    Publication date: October 1, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Ross V. La Fetra, Vilas K. Sridharan, Vydhyanathan Kalyanasundharam, Dean A. Liberty, Amit P. Apte
  • Patent number: 9106260
    Abstract: A processor system as presented herein includes a processor core, cache memory coupled to the processor core, a memory controller coupled to the cache memory, and a system memory component coupled to the memory controller. The system memory component includes a plurality of independent memory channels configured to store data blocks, wherein the memory controller controls the storing of parity bits in at least one of the plurality of independent memory channels. In some implementations, the system memory is realized as a die-stacked memory component.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: August 11, 2015
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: James M. O'Connor, Vilas K. Sridharan, Gabriel H. Loh
  • Publication number: 20150100848
    Abstract: Hard errors in the memory array can be detected and corrected in real-time using reusable entries in an error status buffer. Data may be rewritten to a portion of a memory array and a register in response to a first error in data read from the portion of the memory array. The rewritten data may then be written from the register to an entry of an error status buffer in response to the rewritten data read from the register differing from the rewritten data read from the portion of the memory array.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 9, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Johnsy Kanjirapallil John, Robert Gelinas, Vilas K. Sridharan, Phillip E. Nevius
  • Patent number: 8984368
    Abstract: An integrated circuit includes a memory having an address space and a memory controller coupled to the memory for accessing the address space in response to received memory accesses. The memory controller further accesses a plurality of data elements in a first portion of the address space, and reliability data corresponding to the plurality of data elements in a second portion of the address space.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: March 17, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gabriel H. Loh, Vilas K. Sridharan
  • Publication number: 20140173378
    Abstract: A processor system as presented herein includes a processor core, cache memory coupled to the processor core, a memory controller coupled to the cache memory, and a system memory component coupled to the memory controller. The system memory component includes a plurality of independent memory channels configured to store data blocks, wherein the memory controller controls the storing of parity bits in at least one of the plurality of independent memory channels. In some implementations, the system memory is realized as a die-stacked memory component.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: James M. O'Connor, Vilas K. Sridharan, Gabriel H. Loh
  • Publication number: 20140173379
    Abstract: A method of managing memory includes installing a first cacheline at a first location in a cache memory and receiving a write request. In response to the write request, the first cacheline is modified in accordance with the write request and marked as dirty. Also in response to the write request, a second cacheline is installed that duplicates the first cacheline, as modified in accordance with the write request, at a second location in the cache memory.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Gabriel H. LOH, Vilas K. Sridharan, James M. O'Connor, Jaewoong Sim
  • Publication number: 20140143498
    Abstract: A method of storing stack data in a cache hierarchy is provided. The cache hierarchy comprises a data cache and a stack filter cache. Responsive to a request to access a stack data block, the method stores the stack data block in the stack filter cache, wherein the stack filter cache is configured to store any requested stack data block.
    Type: Application
    Filed: July 18, 2013
    Publication date: May 22, 2014
    Inventors: Lena E. Olson, Yasuko Eckert, Vilas K. Sridharan, James M. O'Connor, Mark D. Hill, Srilatha Manne
  • Publication number: 20140143495
    Abstract: A method of partitioning a data cache comprising a plurality of sets, the plurality of sets comprising a plurality of ways, is provided. Responsive to a stack data request, the method stores a cache line associated with the stack data in one of a plurality of designated ways of the data cache, wherein the plurality of designated ways is configured to store all requested stack data.
    Type: Application
    Filed: July 19, 2013
    Publication date: May 22, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Lena E. Olson, Yasuko Eckert, Vilas K. Sridharan, James M. O'Connor, Mark D. Hill, Srilatha Manne
  • Publication number: 20140143499
    Abstract: A method of way prediction for a data cache having a plurality of ways is provided. Responsive to an instruction to access a stack data block, the method accesses identifying information associated with a plurality of most recently accessed ways of a data cache to determine whether the stack data block resides in one of the plurality of most recently accessed ways of the data cache, wherein the identifying information is accessed from a subset of an array of identifying information corresponding to the plurality of most recently accessed ways; and when the stack data block resides in one of the plurality of most recently accessed ways of the data cache, the method accesses the stack data block from the data cache.
    Type: Application
    Filed: July 18, 2013
    Publication date: May 22, 2014
    Inventors: Lena E. Olson, Yasuko Eckert, Vilas K. Sridharan, James M. O'Connor, Mark D. Hill, Srilatha Manne