Patents by Inventor Vinay B. Chikarmane

Vinay B. Chikarmane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8278718
    Abstract: A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: October 2, 2012
    Assignee: Intel Corporation
    Inventors: Kevin J. Fischer, Vinay B. Chikarmane, Brennan L. Peterson
  • Publication number: 20120068273
    Abstract: A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices.
    Type: Application
    Filed: November 29, 2011
    Publication date: March 22, 2012
    Inventors: Kevin J. Fischer, Vinay B. Chikarmane, Brennan L. Peterson
  • Patent number: 8120119
    Abstract: A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: February 21, 2012
    Assignee: Intel Corporation
    Inventors: Kevin J. Fischer, Vinay B. Chikarmane, Brennan L. Peterson
  • Patent number: 7968952
    Abstract: A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: June 28, 2011
    Assignee: Intel Corporation
    Inventors: Kevin J. Fischer, Vinay B. Chikarmane, Brennan L. Peterson
  • Publication number: 20110133259
    Abstract: A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices.
    Type: Application
    Filed: February 15, 2011
    Publication date: June 9, 2011
    Inventors: Kevin J. Fischer, Vinay B. Chikarmane, Brennan L. Peterson
  • Patent number: 7741219
    Abstract: In one embodiment, a method, comprises forming a diffusion layer on a semiconductor substrate, forming a selectively deposited metal or metal alloy on an aluminum gate structure by removing an aluminum oxide layer from the aluminum gate structure and depositing a zinc layer on the aluminum gate structure by a zincating process, and selectively depositing a sacrificial metal or metal alloy cap on the aluminum gate layer by displacing the zinc layer. This embodiment enables the SAC process flow on devices with Aluminum gates.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: June 22, 2010
    Assignee: Intel Corporation
    Inventors: Vinay B. Chikarmane, Yang Cao
  • Patent number: 7719062
    Abstract: A method for forming a slot contact structure for n-type transistor performance enhancement. A slot contact opening is formed to expose a contact region, and a barrier plug is disposed within a portion of the slot contact opening in order to induce a tensile stress on an adjacent channel region. The remainder of the slot contact opening is filled with a lower resistivity contact metal. Barrier plug deposition temperature can be varied in order to tune the tensile stress on the adjacent channel region.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Kevin J. Fischer, Vinay B. Chikarmane, Brennan L. Peterson
  • Patent number: 7582558
    Abstract: Copper interconnects may be made using the damascene process with reduced copper corrosion. Copper corrosion may be reduced by planarizing through excess copper down to, but not completely through, a copper diffusion barrier layer. The copper diffusion barrier layer may be removed using a different technique. Thereafter, suitable chemicals may be utilized to clean the structure.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: September 1, 2009
    Assignee: Intel Corporation
    Inventors: Vinay B. Chikarmane, Kevin J. Fischer, Brennan L. Peterson
  • Publication number: 20090004857
    Abstract: In one embodiment, a method, comprises forming a diffusion layer on a semiconductor substrate, forming a selectively deposited metal or metal alloy on an aluminum gate structure by removing an aluminum oxide layer from the aluminum gate structure and depositing a zinc layer on the aluminum gate structure by a zincating process, and selectively depositing a sacrificial metal or metal alloy cap on the aluminum gate layer by displacing the zinc layer. This embodiment enables the SAC process flow on devices with Aluminum gates.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Inventors: Vinay B. Chikarmane, Yang Cao
  • Publication number: 20080157208
    Abstract: A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Kevin J. Fischer, Vinay B. Chikarmane, Brennan L. Peterson
  • Publication number: 20080157224
    Abstract: A method for forming a slot contact structure for n-type transistor performance enhancement. A slot contact opening is formed to expose a contact region, and a barrier plug is disposed within a portion of the slot contact opening in order to induce a tensile stress on an adjacent channel region. The remainder of the slot contact opening is filled with a lower resistivity contact metal. Barrier plug deposition temperature can be varied in order to tune the tensile stress on the adjacent channel region.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Kevin J. Fischer, Vinay B. Chikarmane, Brennan L. Peterson
  • Publication number: 20080076246
    Abstract: Embodiments of the invention include apparatuses and methods relating to through contact-opening silicide and barrier layer formation. In one embodiment, a silicide region is formed in a silicon substrate by deposition of a siliciding material in a contact opening and a subsequent anneal.
    Type: Application
    Filed: September 25, 2006
    Publication date: March 27, 2008
    Inventors: Brennan L. Peterson, Vinay B. Chikarmane, Kevin J. Fischer
  • Publication number: 20080014746
    Abstract: Copper interconnects may be made using the damascene process with reduced copper corrosion. Copper corrosion may be reduced by planarizing through excess copper down to, but not completely through, a copper diffusion barrier layer. The copper diffusion barrier layer may be removed using a different technique. Thereafter, suitable chemicals may be utilized to clean the structure.
    Type: Application
    Filed: July 14, 2006
    Publication date: January 17, 2008
    Inventors: Vinay B. Chikarmane, Kevin J. Fischer, Brennan L. Peterson
  • Patent number: 7070687
    Abstract: Apparatus and method for treating a surface of a substrate for electrolytic or electroless plating of metals in integrated circuit manufacturing. In one embodiment the method includes forming a barrier layer on a substrate. A metal-seed layer is then formed on the barrier layer. The method continues by performing in situ surface treatment of the metal-seed layer to form a passivation layer on the metal-seed layer. In another embodiment of a method of this invention, a substrate is provided into an electroplating tool chamber. The substrate has a barrier layer formed thereon, a metal seed layer formed on the barrier layer and a passivation layer formed over the metal seed layer. The method continues by annealing the substrate in forming gas to reduce the passivation layer. A conductive material is deposited on the substrate using an electrolytic plating or electroless plating process.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: July 4, 2006
    Assignee: Intel Corporation
    Inventors: Vinay B. Chikarmane, Chi-Hwa Tsang
  • Patent number: 7001641
    Abstract: Seed layer treatment to remove impurities in the seed layer that might lead to the formation of voids in interconnect circuit features. In one embodiment, the seed layer is heated in a reducing environment. In another embodiment, the seed layer is washed with a surfactant that is compatible with a surfactant used when forming the remainder of the circuit feature on the seed layer. Yet another embodiment combines both techniques.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: February 21, 2006
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Christopher D. Thomas, Vinay B. Chikarmane
  • Publication number: 20040245107
    Abstract: Embodiments of the invention provide methods of reducing electroplating defects by adjusting immersion conditions. For one embodiment, the immersion conditions are adjusted based upon characteristics of the substrate, including feature size. Additionally or alternatively, the immersion conditions may be adjusted based upon aspects of the electroplating process, including motion of the substrate upon immersion. Immersion conditions that may be adjusted in accordance with various embodiments of the invention include entry bias voltage/current, vertical immersion speed, and angle of immersion.
    Type: Application
    Filed: June 3, 2003
    Publication date: December 9, 2004
    Inventors: Guangli Che, Vinay B. Chikarmane, Christopher D. Thomas, Robert I. Wu, Daniel J. Zierath
  • Publication number: 20040188265
    Abstract: Embodiments of the invention provide methods for electroplating a substrate that substantially reduce or eliminate protrusions and decrease WID thickness variations. The number of protrusions formed on the plating surface is highly dependent upon the electroplating current density. Embodiments of the invention vary the electroplating current waveform by implementing an initial current step sufficient to fill substrate features and a terminal current step sufficient to achieve the specified plating thickness while suppressing protrusions and within die thickness variations.
    Type: Application
    Filed: March 25, 2003
    Publication date: September 30, 2004
    Inventors: Yang Cao, Vinay B. Chikarmane, Rajiv Rastogi, Daniel J. Zierath
  • Publication number: 20040058139
    Abstract: Seed layer treatment to remove impurities in the seed layer that might lead to the formation of voids in interconnect circuit features. In one embodiment, the seed layer is heated in a reducing environment. In another embodiment, the seed layer is washed with a surfactant that is compatible with a surfactant used when forming the remainder of the circuit feature on the seed layer. Yet another embodiment combines both techniques.
    Type: Application
    Filed: September 23, 2002
    Publication date: March 25, 2004
    Inventors: Valery M. Dubin, Christopher D. Thomas, Vinay B. Chikarmane
  • Publication number: 20030034251
    Abstract: Apparatus and method for treating a surface of a substrate for electrolytic or electroless plating of metals in integrated circuit manufacturing. In one embodiment the method includes forming a barrier layer on a substrate. A metal-seed layer is then formed on the barrier layer. The method continues by performing in situ surface treatment of the metal-seed layer to form a passivation layer on the metal-seed layer.
    Type: Application
    Filed: August 14, 2001
    Publication date: February 20, 2003
    Inventors: Vinay B. Chikarmane, Chi-Hwa Tsang
  • Patent number: 5804251
    Abstract: A method for forming an aluminum or aluminum alloy plug in the fabrication of a semiconductor device. An opening is formed in a wafer. A titanium wetting layer is then deposited over the wafer and lines the sidewalls and bottom of the opening. The opening is then filled with aluminum in two steps, both steps being performed at approximately the same temperature. The first aluminum deposition step is performed at a first (slower) deposition rate. The second aluminum deposition step is performed at the same temperature as the first deposition step but at a different (or second/faster) deposition rate until the opening is completely filled.
    Type: Grant
    Filed: April 25, 1997
    Date of Patent: September 8, 1998
    Assignee: Intel Corporation
    Inventors: Jick M. Yu, Vinay B. Chikarmane