Patents by Inventor Vincent A. Pillai
Vincent A. Pillai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240084769Abstract: A connector block that directs fuel from an outer fuel line to an inner fuel line. The connector block includes an inlet that couples to the outer fuel line, an outlet that coupled to the inner fuel line, and a fuel accumulator fluidly coupled to the inlet and the outlet. The fuel accumulator directs the fuel from the inlet to the outlet.Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Applicant: CUMMINS INC.Inventors: Kieran J. Richards, Brandon Glover, Vincent Denoyelle, Jacques L. Vincent, Raghuvaran Arumugam, Satya Dinakar Vyseetty, Joseph A. Worthington, Abhishek Mehrotra, Deepak Pillai, Todd S. Manley
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Patent number: 5840622Abstract: Phase mask laser machining procedures for fabricating high density fine pattern feature electrical interconnection structures. Conductor patterns are fabricated using a phase mask laser patterned dielectric layer as a conductor wet etch masking layer, or by subtractively removing metal using holographic phase mask laser micromachining. In accordance with the present invention, a substrate is provided, a first layer of dielectric material is formed on the substrate, a metal layer is formed on the first layer of dielectric material, and a second layer of dielectric material is then formed on the metal layer. A phase mask is disposed above the second layer of dielectric material that has a predefined phase pattern therein defining a metal conductor pattern that corresponds to an interconnect structure. The second layer of dielectric material is then processed using the phase mask to form the interconnect structure.Type: GrantFiled: August 27, 1996Date of Patent: November 24, 1998Assignee: Raytheon CompanyInventors: Robert S. Miles, Philip A. Trask, Vincent A. Pillai
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Patent number: 5827775Abstract: Phase mask laser machining procedures for fabricating high density fine pattern feature electrical interconnection structures. Conductor patterns are fabricated using a phase mask laser patterned dielectric layer as a conductor wet etch masking layer, or by subtractively removing metal using holographic phase mask laser micromachining. In accordance with the present invention, a substrate is provided, a first layer of dielectric material is formed on the substrate, a metal layer is formed on the first layer of dielectric material, and a second layer of dielectric material is then formed on the metal layer. A phase mask is disposed above the second layer of dielectric material that has a predefined phase pattern therein defining a metal conductor pattern that corresponds to an interconnect structure. The second layer of dielectric material is then processed using the phase mask to form the interconnect structure.Type: GrantFiled: November 12, 1997Date of Patent: October 27, 1998Assignee: Raytheon ComapnyInventors: Robert S. Miles, Philip A. Trask, Vincent A. Pillai
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Patent number: 5691245Abstract: Methods of forming two-sided high density multilayer interconnect (HDMI) structures on a relatively large carrier and subsequently releasing and removing one or more structures to provide useable flexible interconnects or decals. In general, a carrier is provided and a release layer is formed on the carrier. Flexible high density multilayer interconnect structures are fabricated on the release layer. The release layer is processed to release and remove one or more flexible HDMI structures from the carrier. The carrier may be an ultraviolet transparent substrate, such as quartz, for example, and the release layer may be a polyimide layer. The HDMI structures are released by irradiating the release layer through the transparent carrier using ultraviolet radiation from an ultraviolet radiation source. Alternatively, a silicon carrier may be used that has a metal or silicon dioxide release layer formed thereon.Type: GrantFiled: October 28, 1996Date of Patent: November 25, 1997Assignee: HE Holdings, Inc.Inventors: Gabriel G. Bakhit, Vincent A. Pillai, George Averkiou, Philip A. Trask
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Patent number: 5474956Abstract: A method of patterning a metallized substrate using a thin partially cured etch block layer. In accordance with the method, a substrate is provided and a layer of metal, such as aluminum, is deposited on the substrate. A thin layer of organic dielectric material, such as polyimide, is deposited over the layer of metal. The thin layer of organic dielectric material is deposited to a thickness on the order one micron, for example, which is thin enough to have etch resistance when acting as an etch block layer for subsequent wet etch patterning of the layer of metal, and thick enough to have no pinhole defects. The deposited thin organic dielectric layer is then partially cured. The underlying layer of metal is then patterned and wet etched using the partially cured thin organic dielectric material as the blocking layer. An additional thick layer of organic dielectric material is then deposited or coated over the patterned layer of metal and partially cured organic dielectric layer.Type: GrantFiled: March 14, 1995Date of Patent: December 12, 1995Assignee: Hughes Aircraft CompanyInventors: Philip A. Trask, Vincent A. Pillai
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Electrical interconnection substrate with both wire bond and solder contacts, and fabrication method
Patent number: 5445311Abstract: An electrical interconnection substrate (20) is prepared to receive both wire bonded and soldered connections (60,64,66) by forming a dielectric solder mask (30) over the substrate (20), with openings (36) in the mask (30) to expose the contact pads (22) for which soldered connections are desired. The substrate (20) is exposed to a molten solder alloy (44) in a wave soldering process that dissolves the wire bonding material (28) (preferably gold) from the exposed pads (22) and deposits solder bonding pads (52) in its place. Excess solder is then removed from the substrate, and openings (54) are formed through the solder mask (30) to expose the wire bond contact pads (22'). The selective dissolving of gold bonding layers (28) and their replacement by solder pads (52) prevents the establishment of brittle gold-solder intermetallics, and the deposited solder (52) requires no further heat treatment for correct alloy formation.Type: GrantFiled: October 13, 1994Date of Patent: August 29, 1995Assignee: Hughes Aircraft CompanyInventors: Philip A. Trask, Vincent A. Pillai, Thomas J. Gierhart -
Patent number: 5311404Abstract: An electrical interconnection substrate (20) is prepared to receive both wire bonded and soldered connections (60,64,66) by forming a dielectric solder mask (30) over the substrate (20), with openings (36) in the mask (30) to expose the contact pads (22) for which soldered connections are desired. The substrate (20) is exposed to a molten solder alloy (44) in a wave soldering process that dissolves the wire bonding material (28) (preferably gold) from the exposed pads (22) and deposits solder bonding pads (52) in its place. Excess solder is then removed from the substrate, and openings (54) are formed through the solder mask (30) to expose the wire bond contact pads (22'). The selective dissolving of gold bonding layers (28) and their replacement by solder pads (52) prevents the establishment of brittle gold-solder intermetallics, and the deposited solder (52) requires no further heat treatment for correct alloy formation.Type: GrantFiled: June 30, 1992Date of Patent: May 10, 1994Assignee: Hughes Aircraft CompanyInventors: Philip A. Trask, Vincent A. Pillai, Thomas J. Gierhart
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Patent number: 5034091Abstract: A via (26) is formed through a dielectric layer (8) separating two conductive layers (16,28) by establishing a laterally erodible mask (18) over the dielectric (8), with a window (24) over the desired via location. The mask (18) and exposed dielectric material (8) are eroded simultaneously, preferably by reactive ion etching, producing a via (26) through the dielectric (8) which expands laterally as vertical erosion proceeds. The erosion conditions, the materials for the mask (18) and dielectric (8), and the initial window (24) taper are selected so that the final via (26) is tapered at an angle of less than about 45.degree. to the lower metal layer (6), and preferably about 30.degree.-45.degree., to enable a generally uniform width for the upper metallization (28) in the via (26).Type: GrantFiled: April 27, 1990Date of Patent: July 23, 1991Assignee: Hughes Aircraft CompanyInventors: Philip A. Trask, Gabriel G. Bakhit, Vincent A. Pillai, Kirk R. Osborne, Kathryn J. Berg, Gary B. Warren