Abstract: Methods, systems, and apparatus for power consumption control in an electronic system is disclosed. A voltage of a voltage rail coupled between a power management system and the electronic system to a power consumption trigger voltage is compared. Based on the voltage of the voltage rail being below the power consumption trigger voltage, power consumption by the electronic system is increased to reduce the voltage of the voltage rail during a power down of the electronic system. A voltage output by a power source which is provided as an input to the power management system is detected to be at a nominal voltage after increasing the power consumption. Based on the detection, a regulated voltage is provided to the voltage rail to power up the electronic system.

Abstract: An address to perform a memory operation on a memory location in a rectangular frame buffer is received. A determination is made whether the received address identifies a memory location in a non-rectangular frame buffer corresponding to a memory location in the rectangular frame buffer. Based on the determination that the received address identifies the memory location in the non-rectangular buffer, the memory operation on the memory location in the non-rectangular buffer is performed based on the translated address. Based on the determination that the received address does not identify the memory location in the non-rectangular buffer, the memory operation in the non-rectangular frame buffer is not performed.

Abstract: Embodiments of a method and an apparatus for power management are disclosed. In an embodiment, a power management system includes a capacitor, control logic configured to determine a wait time in response to a comparison of a voltage of the capacitor to a threshold voltage and to initiate a startup upon expiration of the wait time, and a control circuit configured to charge the capacitor, discharge the capacitor, and provide the voltage of the capacitor to the control logic.

Abstract: A microcontroller comprising a first integrated circuit configured to receive power from a power supply comprising a second integrated circuit via at least one power input terminal and wherein at least one communication terminal provides for communication between the microcontroller and the power supply, wherein the microcontroller is configured to provide for encrypted communication between the power supply and the microcontroller based on a pre-shared encryption key, the encrypted communication configured to provide for authentication of the identity of the power supply and, if the power supply passes the authentication, the microcontroller is configured to operate in a normal mode and receive said power from the power supply, and if the power supply fails authentication, the microcontroller is configured to enter a tamper mode.

Abstract: A system includes a video generation circuit (102) to generate first graphics information, a display circuit (112) to display the graphics information, and a low voltage differential signaling (LVDS) (120) video interface to couple graphics information from the video generation circuit to the display circuit. The display circuit can determine that a first channel (204) of the LVDS video interface is corrupted. In response, the display circuit provides a remediation signal (205) to direct the video generation circuit (102) to operate in an alternative operating mode (208).

Abstract: A peak current detector is integrated into a power supply, such as a power management integrated circuit, to detect glitch attacks imposed on the power rails inside the power supply. Integrated circuitry being supplied by the power supply periodically checks the state of the power supply via a secure communication channel to obtain the detected peak current values, which allow the integrated circuitry to detect those attacks and react accordingly to any possible threats.

Abstract: A frame buffer having a size of one video frame of a video stream is provided. The video stream has a source frame rate. Image data units of the video stream are written consecutively to the frame buffer in accordance with a circular buffering scheme and in real-time response to the video stream. Image data units are read from the frame buffer in accordance with the circular buffering scheme with a frame rate that is twice the source frame rate so as to generate a target video stream having a frame rate which is twice the source frame rate. The frame buffer can be used in a real-time video system, for example in a vehicle.

Abstract: A microcontroller comprising a first integrated circuit configured to receive power from a power supply comprising a second integrated circuit via at least one power input terminal and wherein at least one communication terminal provides for communication between the microcontroller and the power supply, wherein the microcontroller is configured to provide for encrypted communication between the power supply and the microcontroller based on a pre-shared encryption key, the encrypted communication configured to provide for authentication of the identity of the power supply and, if the power supply passes the authentication, the microcontroller is configured to operate in a normal mode and receive said power from the power supply, and if the power supply fails authentication, the microcontroller is configured to enter a tamper mode.

Abstract: The invention provides an apparatus and method which allows identification of the system which provided images for each pixel of a touchscreen display which displays merged images of arbitrary shapes supplied from a plurality of systems. It further allows routing of user inputs to the appropriate system for further processing. Colour keying may be used to superimpose one image onto another. The invention finds particular application in the automotive field where images produced by an infotainment system may be merged with those produced by a mobile phone onto the in-vehicle display screen.

Abstract: A system includes a video generation circuit (102) to generate first graphics information, a display circuit (112) to display the graphics information, and a low voltage differential signaling (LVDS) (120) video interface to couple graphics information from the video generation circuit to the display circuit. The display circuit can determine that a first channel (204) of the LVDS video interface is corrupted. In response, the display circuit provides a remediation signal (205) to direct the video generation circuit (102) to operate in an alternative operating mode (208).

Abstract: A layer selection module for a graphics display component, and method therefor. The layer selection module is arranged to identify a set M of active layers to be blended for a pixel, configure a display controller to generate composite pixel data for the pixel based on a subset N of up to n layers from the set M, determine whether a number m of active layers in the set M exceeds n, and output an indication of which active layers within the set M were excluded from the subset N, if it is determined that the number m of layers in the set M exceeds n.

Abstract: A display control apparatus comprising at least one memory element within which image data is stored, at least one display controller arranged to read from the, or each, memory element the image data and to output display data generated from the read image data to at least one display device. The display control apparatus further comprises at least one interface component via which the display controller is arranged to read image data from the memory element. The display control apparatus further comprises at least one interface bandwidth control component arranged to measure image data flow over the interface component from the memory element to the display controller, and configure a bandwidth for image data flow over the interface component from the memory element to the display controller based at least partly on the measured image data flow.

Abstract: In a video system, a video source, e.g., a camera, provides a source video stream. The source video stream comprises a stream of image data units. A buffer control unit writes the image data units consecutively to a circular buffer. A display control unit reads the image data units consecutively from the circular buffer to generate a target video stream in accordance with a read delay. The display control unit comprises a feedback loop which controls timing of the operation of reading the image data units from the circular buffer so as to reduce a difference between the read delay and a reference delay. The video system may, for example, be installed in a vehicle, e.g., for providing a driver with a live view from a camera.

Abstract: A display processor device is for processing display image data by overlaying a multitude of image layers. Pixel values of at least one of the image layers are stored in a memory and may comprise pixels values having a single predefined value, such as transparency. The display processor has a fetch unit for selectively fetching stored pixel values from the memory by skipping stored pixels values having the single predefined value according to a fetch mask indicative of pixels values having the single predetermined value. Advantageously the bandwidth for accessing the memory is reduced, because less pixel data values need be retrieved. Power consumption may be reduced, and slower memories may be applied.

Abstract: A display controller comprises a plurality of channels for fetching data from a memory, a plurality of buffers coupled to the channels for receiving the fetched data from the channels, a buffer controller for controlling the buffers and the channels, and a processing unit coupled to the buffers, the display and buffer controller for receiving the data from the buffers, outputting a control signal to the display based on the received data, and controlling the buffer controller, respectively. Each buffer has a respective fixed memory capacity for storing the fetched data. The processing unit activates layers in the output image for displaying an output image on the display. The channels correspond to associated layers. The buffer controller adds to the respective fixed memory capacity of a particular buffer associated to an activated layer, one further fixed memory capacity of at least one further buffer associated to an inactive layer.

Abstract: The invention provides an apparatus and method for checking the integrity of visual display information and has particular application to checking images displayed in an automotive vehicle, such images containing safety critical information. The image intensity is checked only to an extent commensurate with a human being able to interpret its correct meaning. Hence, images which are defective in some way yet still recognisable by the human eye are not classified as failures. In one embodiment, a part of the image containing safety critical information is segmented into smaller areas and the luminance of pixels in each segmented area is compared with a threshold brightness level and a threshold darkness level. A histogram for each area is generated and compared with a reference.

Abstract: A data processing system comprising at least a memory unit, a first client connected to the memory unit, and a second client connected to the memory unit is proposed. The first client may comprise a first memory access unit and an information unit. The first memory access unit may read data from or write data to the memory unit at a first data rate. The information unit may update internal data correlating with a minimum required value of the first data rate. The second client may comprise a second memory access unit and a data rate limiting unit. The second memory access unit may read data from or write data to the memory unit at a second data rate. The data rate limiting unit may limit the second data rate in dependence on the internal data. The first memory access unit may, for example, read data packets sequentially from the memory unit, and the information unit may update the internal data at least per data packet. A method of controlling access to a shared memory unit is also proposed.

Abstract: A layer selection module for a graphics display component, and method therefor. The layer selection module is arranged to identify a set M of active layers to be blended for a pixel, configure a display controller to generate composite pixel data for the pixel based on a subset N of up to n layers from the set M, determine whether a number m of active layers in the set M exceeds n, and output an indication of which active layers within the set M were excluded from the subset N, if it is determined that the number m of layers in the set M exceeds n.

Abstract: The present application relates to an interconnect system comprising a video signal transmitter and video signal receiver for transmitting a stream of N-symbol data signals over an error prone wired parallel bus having at least N data signal lines. A line scrambler at the video signal transmitter is configured to accept an N-symbol data signal having a sequence of data symbols in a predefined order and to output a permuted sequence of data symbols in accordance with a permutation. The line de-scrambler at the video signal receiver is configured to accept the permuted sequence of data symbols at its input terminal and to restore the predefined order of data symbols from the permuted sequence of data symbols in accordance with the corresponding reverse permutation.

Abstract: The present application relates to an interconnect system for transmitting a stream of N-symbol data signals, which comprises a parallel data signal line bus, a line scrambler, a line de-scrambler and a defect detector. The defect detector is configured to detect one or more defective data signal lines. The line scrambler 110 is configured to accept an N-symbol data signal d having a sequence of data symbols in a predefined order and to output a permuted sequence d? of data symbols at its N output terminals oj. The line de-scrambler is configured to accept the permuted sequence d? of data symbols at its input terminal i?j, to restore the predefined order of the data symbols from the permuted sequence d? of data symbols; and to output the restored N-symbol data signal d comprising a sequence of data symbols in the predefined order.