Patents by Inventor Vincent Gambin

Vincent Gambin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9735545
    Abstract: A vertical cavity surface emitting laser (VCSEL) including a substrate and a bottom distributed Bragg reflector (DBR) having a plurality of layers deposited on the substrate. The VCSEL also includes a first charge confining layer deposited on the bottom DBR, an active region deposited on the first charge confining layer, and a second charge confining layer deposited on the active region. A current blocking layer is provided on the second charge confining layer, and a top epitaxial DBR including a plurality of top epitaxial DBR layers is deposited on the current blocking layer. A top electrode is deposited on the top epitaxial DBR, a bottom electrode is deposited on the bottom DBR and adjacent to the active region, and a top dielectric DBR is deposited on the top epitaxial DBR and the top electrode.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: August 15, 2017
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Yaochung Chen, Vincent Gambin, Xianglin Zeng
  • Patent number: 9484284
    Abstract: A MMIC power amplifier circuit assembly comprised of a SiC substrate having a plurality of microchannels formed therein, where a diamond layer is provided within each of the microchannels. A plurality of GaN HEMT devices are provided on the substrate where each HEMT device is positioned directly opposite to a microchannel. A silicon manifold is coupled to the substrate and includes a plurality of micro-machined channels formed therein that include a jet impingement channel positioned directly adjacent each microchannel, a return channel directly positioned adjacent to each microchannel, a supply channel supplying a cooling fluid to the impingement channels and a return channel collecting heated cooling fluid from the supply channels so that an impingement jet is directed on to the diamond layer for removing heat generated by the HEMT devices.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: November 1, 2016
    Assignees: Northrop Grumman Systems Corporation, General Electric Company
    Inventors: Vincent Gambin, Benjamin D. Poust, Dino Ferizovic, Stanton E. Weaver, Gary D. Mandrusiak
  • Patent number: 9196703
    Abstract: A method for fabricating a semiconductor device, such as a GaN high electron mobility transistor (HEMT) device, including etching a thermal via into a back-side of a semiconductor substrate and depositing a diamond nucleation seed layer across the back-side of the substrate. The method further includes coating the diamond nucleation with a mask layer and removing mask material outside of the thermal via on the planar portions of the back-side of the substrate. The method includes removing portions of the diamond nucleation layer on the planar portions and then removing the remaining portion of the mask material in the thermal via. The method then includes depositing a bulk diamond layer within the thermal via on the remaining portion of the diamond nucleation layer so that diamond only grows in the thermal via and not on the planar portions of the substrate.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: November 24, 2015
    Assignees: Northrop Grumman Systems Corporation, The United States of America, as Represented by the Secretary of the Navy, The Regents of the University of California
    Inventors: Karl D. Hobart, Tatyana I. Feygelson, Eugene I. Imhoff, Travis J. Anderson, Joshua D. Caldwell, Andrew D. Koehler, Bradford B. Pate, Marko J. Tadjer, Rajinder S. Sandhu, Vincent Gambin, Gregory Lewis, Ioulia Smorchkova, Mark Goorsky, Jeff McKay
  • Publication number: 20150056763
    Abstract: A method for fabricating a semiconductor device, such as a GaN high electron mobility transistor (HEMT) device, including etching a thermal via into a back-side of a semiconductor substrate and depositing a diamond nucleation seed layer across the back-side of the substrate. The method further includes coating the diamond nucleation with a mask layer and removing mask material outside of the thermal via on the planar portions of the back-side of the substrate. The method includes removing portions of the diamond nucleation layer on the planar portions and then removing the remaining portion of the mask material in the thermal via. The method then includes depositing a bulk diamond layer within the thermal via on the remaining portion of the diamond nucleation layer so that diamond only grows in the thermal via and not on the planar portions of the substrate.
    Type: Application
    Filed: August 20, 2014
    Publication date: February 26, 2015
    Inventors: Karl D. Hobart, Tatyana I. Feygelson, Eugene A. Imhoff, Travis J. Anderson, Joshua D. Caldwell, Andrew D. Koehler, Bradford B. Pate, Marko J. Tadjer, Randijer S. Sandhu, Vincent Gambin, Gregory Lewis, Ioulia Smorchkova, Mark Goorsky, Jeff McKay
  • Patent number: 8710511
    Abstract: An N-face GaN HEMT device including a semiconductor substrate, a buffer layer including AlN or AlGaN deposited on the substrate, a barrier layer including AlGaN or AlN deposited on the buffer layer and a GaN channel layer deposited on the barrier layer. The channel layer, the barrier layer and the buffer layer create a two-dimensional electron gas (2-DEG) layer at a transition between the channel layer and the barrier layer.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: April 29, 2014
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Vincent Gambin, Xing Gu, Benjamin Heying
  • Patent number: 8575657
    Abstract: A GaN high electron mobility transistor (HEMT) device having a silicon carbide substrate including a top surface and a bottom surface, where the substrate further includes a via formed through the bottom surface and into the substrate. The device includes a plurality of epitaxial layers provided on the top surface of the substrate, a plurality of device layers provided on the epitaxial layers, and a diamond layer provided within the via.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: November 5, 2013
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Vincent Gambin, Rajinder Sandhu, Benjamin Poust, Michael Wojtowicz
  • Publication number: 20130248879
    Abstract: A GaN high electron mobility transistor (HEMT) device having a silicon carbide substrate including a top surface and a bottom surface, where the substrate further includes a via formed through the bottom surface and into the substrate. The device includes a plurality of epitaxial layers provided on the top surface of the substrate, a plurality of device layers provided on the epitaxial layers, and a diamond layer provided within the via.
    Type: Application
    Filed: March 20, 2012
    Publication date: September 26, 2013
    Applicant: Northrop Grumman Systems Corporation
    Inventors: Vincent Gambin, Rajinder Sandhu, Benjamin Poust, Michael Wojtowicz
  • Patent number: 8431962
    Abstract: A nitride-based FET device that provides reduced electron trapping and gate current leakage. The device includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current leakage. The device includes semiconductor device layers deposited on a substrate. A plurality of passivation layers are deposited on the semiconductor device layers, where at least two of the layers are made of a different dielectric material to provide an etch stop. One or more of the passivation layers can be removed using the interfaces between the layers as an etch stop so that the distance between the gate terminal and the semiconductor device layers can be tightly controlled, where the distance can be made very thin to increase device performance and reduce gate current leakage.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: April 30, 2013
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Benjamin Heying, Ioulia Smorchkova, Vincent Gambin, Robert Coffie
  • Publication number: 20130026489
    Abstract: An N-face GaN HEMT device including a semiconductor substrate, a buffer layer including AlN or AlGaN deposited on the substrate, a barrier layer including AlGaN or AlN deposited on the buffer layer and a GaN channel layer deposited on the barrier layer. The channel layer, the barrier layer and the buffer layer create a two-dimensional electron gas (2-DEG) layer at a transition between the channel layer and the barrier layer.
    Type: Application
    Filed: July 29, 2011
    Publication date: January 31, 2013
    Applicant: Northrop Grumman Systems Corporation
    Inventors: Vincent Gambin, Xing Gu, Benjamin Heying
  • Patent number: 7893423
    Abstract: A device and method associated with carbon nanowires, such as single walled carbon nanowires having a high degree of alignment are set forth herein. A catalyst layer is deposited having a predetermined crystallographic configuration so as to control a growth parameter, such as an alignment direction, a diameter, a crystallinity and the like of the carbon nanowire. The catalyst layer is etched to expose a sidewall portion. The carbon nanowire is nucleated from the exposed sidewall portion. An electrical circuit device can include a single crystal substrate, such as Silicon, and a crystallographically oriented catalyst layer on the substrate having an exposed sidewall portion. In the device, carbon nanowires are disposed on the single crystal substrate aligned in a direction associated with the crystallographic properties of the catalyst layer.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: February 22, 2011
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Vincent Gambin, Roger Su-Tsung Tsai
  • Publication number: 20100127240
    Abstract: A device and method associated with carbon nanowires, such as single walled carbon nanowires having a high degree of alignment are set forth herein. A catalyst layer is deposited having a predetermined crystallographic configuration so as to control a growth parameter, such as an alignment direction, a diameter, a crystallinity and the like of the carbon nanowire. The catalyst layer is etched to expose a sidewall portion. The carbon nanowire is nucleated from the exposed sidewall portion. An electrical circuit device can include a single crystal substrate, such as Silicon, and a crystallographically oriented catalyst layer on the substrate having an exposed sidewall portion. In the device, carbon nanowires are disposed on the single crystal substrate aligned in a direction associated with the crystallographic properties of the catalyst layer.
    Type: Application
    Filed: January 21, 2010
    Publication date: May 27, 2010
    Applicant: NORTHROP GRUMMAN SPACE & MISSION SYSTEMS CORP.
    Inventors: Vincent Gambin, Roger Su-Tsung Tsai
  • Patent number: 7678672
    Abstract: A device and method associated with carbon nanowires, such as single walled carbon nanowires having a high degree of alignment are set forth herein. A catalyst layer is deposited having a predetermined crystallographic configuration so as to control a growth parameter, such as an alignment direction, a diameter, a crystallinity and the like of the carbon nanowire. The catalyst layer is etched to expose a sidewall portion. The carbon nanowire is nucleated from the exposed sidewall portion. An electrical circuit device can include a single crystal substrate, such as Silicon, and a crystallographically oriented catalyst layer on the substrate having an exposed sidewall portion. In the device, carbon nanowires are disposed on the single crystal substrate aligned in a direction associated with the crystallographic properties of the catalyst layer.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: March 16, 2010
    Assignee: Northrop Grumman Space & Mission Systems Corp.
    Inventors: Vincent Gambin, Roger Su-Tsung Tsai
  • Publication number: 20100029063
    Abstract: A device and method associated with carbon nanowires, such as single walled carbon nanowires having a high degree of alignment are set forth herein. A catalyst layer is deposited having a predetermined crystallographic configuration so as to control a growth parameter, such as an alignment direction, a diameter, a crystallinity and the like of the carbon nanowire. The catalyst layer is etched to expose a sidewall portion. The carbon nanowire is nucleated from the exposed sidewall portion. An electrical circuit device can include a single crystal substrate, such as Silicon, and a crystallographically oriented catalyst layer on the substrate having an exposed sidewall portion. In the device, carbon nanowires are disposed on the single crystal substrate aligned in a direction associated with the crystallographic properties of the catalyst layer.
    Type: Application
    Filed: January 16, 2007
    Publication date: February 4, 2010
    Applicant: Northrop Grumman Space & Mission Systems Corporation
    Inventors: Vincent Gambin, Roger Su-Tsung Tsai
  • Patent number: 7645626
    Abstract: In connection with an optical-electronic semiconductor device, improved photoluminescent output is provided at wavelengths approaching and beyond 1.3 ?m. According to one aspect, a multiple quantum well strain compensated structure is formed using a GaInNAs-based quantum well laser diode with GaNAs-based barrier layers. By growing tensile-strained GaNAs barrier layers, a larger active region with multiple quantum wells can be formed increasing the optical gain of the device. In example implementations, both edge emitting laser devices and vertical cavity surface emitting laser (VCSEL) devices can be grown with at least several quantum wells, for example, nine quantum wells, and with room temperature emission approaching and beyond 1.3 ?m.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: January 12, 2010
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Wonill Ha, Vincent Gambin, James S. Harris
  • Patent number: 7632726
    Abstract: A method for fabricating a nitride-based FET device that provides reduced electron trapping and gate current leakage. The fabrication method provides a device that includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current leakage. Semiconductor device layers are deposited on a substrate. A plurality of passivation layers are deposited on the semiconductor device layers, where at least two of the layers are made of a different dielectric material to provide an etch stop. One or more of the passivation layers can be removed using the interfaces between the layers as an etch stop so that the distance between the gate terminal and the semiconductor device layers can be tightly controlled, where the distance can be made very thin to increase device performance and reduce gate current leakage.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: December 15, 2009
    Assignee: Northrop Grumman Space & Mission Systems Corp.
    Inventors: Benjamin Heying, Ioulia Smorchkova, Vincent Gambin, Robert Coffie
  • Publication number: 20090148985
    Abstract: A method for fabricating a nitride-based FET device that provides reduced electron trapping and gate current leakage. The fabrication method provides a device that includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current leakage. Semiconductor device layers are deposited on a substrate. A plurality of passivation layers are deposited on the semiconductor device layers, where at least two of the layers are made of a different dielectric material to provide an etch stop. One or more of the passivation layers can be removed using the interfaces between the layers as an etch stop so that the distance between the gate terminal and the semiconductor device layers can be tightly controlled, where the distance can be made very thin to increase device performance and reduce gate current leakage.
    Type: Application
    Filed: December 7, 2007
    Publication date: June 11, 2009
    Applicant: Northrop Grumman Space & Mission Systems Corp.
    Inventors: Benjamin Heying, Ioulia Smorchkova, Vincent Gambin, Robert Coffie
  • Publication number: 20090146224
    Abstract: A nitride-based FET device that provides reduced electron trapping and gate current leakage. The device includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current leakage. The device includes semiconductor device layers deposited on a substrate. A plurality of passivation layers are deposited on the semiconductor device layers, where at least two of the layers are made of a different dielectric material to provide an etch stop. One or more of the passivation layers can be removed using the interfaces between the layers as an etch stop so that the distance between the gate terminal and the semiconductor device layers can be tightly controlled, where the distance can be made very thin to increase device performance and reduce gate current leakage.
    Type: Application
    Filed: December 7, 2007
    Publication date: June 11, 2009
    Applicant: Northrop Grumman Space & Mission Systems Corp.
    Inventors: Benjamin Heying, Ioulia Smorchkova, Vincent Gambin, Robert Coffie
  • Publication number: 20080199993
    Abstract: An improved method for fabricating an HEMT device having active device layers deposited on a semiconductor substrate. In an embodiment, the improved method comprises the steps of depositing an AlN layer over the active device layers using a relatively low temperature vacuum process to form an amorphous layer protecting the active device layers from unnecessary exposure to fabrication processes, and selectively forming openings in the AlN layer to expose portions of the active device layers for imminent process steps.
    Type: Application
    Filed: February 21, 2007
    Publication date: August 21, 2008
    Inventors: Benjamin Heying, Ioulia Smorchkova, Vincent Gambin, Robert Coffie
  • Patent number: 7084040
    Abstract: Formation of a regrowth layer of a Group III–V semiconductor material is facilitated by prior formation of an intermediate layer, selected primarily for its smooth morphology properties. The intermediate layer is formed over an underlying substrate and over a dielectric layer formed over portions of the substrate. The intermediate layer maintains the monocrystalline properties of the underlying substrate in regions other than those covered by the dielectric layer, and improves the electrical and morphology properties of the regrowth layer formed over the intermediate layer.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: August 1, 2006
    Assignee: Northrop Grumman Corp.
    Inventors: Vincent Gambin, Donald J. Sawdai
  • Publication number: 20060039432
    Abstract: In connection with an optical-electronic semiconductor device, improved photoluminescent output is provided at wavelengths approaching and beyond 1.3 ?m. According to one aspect, a multiple quantum well strain compensated structure is formed using a GaInNAs-based quantum well laser diode with GaNAs-based barrier layers. By growing tensile-strained GaNAs barrier layers, a larger active region with multiple quantum wells can be formed increasing the optical gain of the device. In example implementations, both edge emitting laser devices and vertical cavity surface emitting laser (VCSEL) devices can be grown with at least several quantum wells, for example, nine quantum wells, and with room temperature emission approaching and beyond 1.3 ?m.
    Type: Application
    Filed: December 30, 2004
    Publication date: February 23, 2006
    Inventors: Wonill Ha, Vincent Gambin, James Harris