Abstract: A Swertia chirata extract obtained by extracting with supercritical CO2 an alcoholic extract of Swertia chirata, and to a cosmetic composition including such an extract having in particular an anti-ageing effect for the skin. Also, administering such an extract in a cosmetic method for preventing and/or reducing skin ageing and a cosmetic method for hydrating the skin and/or improving the barrier function of the skin.

Abstract: An alcoholic extract of Citrus depressa peels, a cosmetic composition including such an extract having in particular a preventive effect against desquamation of the skin, as well as its method of preparation. Also, the method of limiting/protecting against excessive desquamation and contributing to skin comfort by applying the alcoholic extract of Citrus depressa peels to the skin.

Abstract: A piece of equipment for production of a closed-section cross-member configured to connect two longitudinal arms of a flexible axle of a motor vehicle. The equipment includes at least one matrix configured to cooperate with a punch to form a torsion area of a certain length on the closed section of the cross-member and a mechanism to maintain the cross-member in position. The length of the matrix and/or the punch can be adapted to adapt the length of the torsion area.

Abstract: A processor is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. A coefficient data pointer is provided for accessing coefficient data for use in a multiply-accumulate (MAC) unit. Monitoring circuitry determines when the coefficient data pointer is modified (step 1104). When an instruction is executed (step 1102) that requires a coefficient datum from memory in accordance with the coefficient data pointer, a memory access is inhibited (step 1108) if the coefficient data pointer has not been modified since the last time a memory fetch was made in accordance with the coefficient data pointer and the previously fetched coefficient datum is reused.

Abstract: A processing engine 10 for executing instructions in parallel comprises an instruction buffer 600 for holding at least two instructions, with the first instruction 602 in a first position and the second instruction 604 in a second position. A first decoder 612 provides decoding of the first instruction and generates first control signals. The first control signals include first resource control signals, first address generation control signals, and a first validity signal indicative of the validity of the first instruction in the first position. A second decoder 614 provides decoding of the second instruction and generates second control signals. The second control signals include second resource control signals, second address generation control signals, and a second validity signal indicative of the validity of the second instruction in the second position.

Abstract: A processing engine 10 includes an instruction buffer 502 operable to buffer single and compound instructions pending execution. A decode mechanism is configured to decode instructions from the instruction buffer. The decode mechanism is arranged to respond to a predetermined tag in a tag field of an instruction, which predetermined tag is representative of the instruction being a compound instruction formed from separate programmed memory instructions. The decode mechanism is operable in response to the predetermined tag to decode at least first data flow control for a first programmed instruction and second data flow control for a second programmed instruction. The use of compound instructions enables effective use of the bandwidth available within the processing engine. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions.

Abstract: A processor (100) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit (106), a program flow control unit (108), an address/data flow unit (110), a data computation unit (112), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit (104) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor.

Abstract: An apparatus and method for manufacturing a reinforcement member wherein the reinforcement member includes a reelable steel tape being incorporated into concrete. The faces of the steel tape each include substantially rectalinear ribs arranged in at least one longitudinal row, the ribs being substantially parallel to each other and inclined with respect to the longitudinal direction of the tape. The ribs of one of the faces of the tape are symmetrical with respect to the ribs of the other of the faces of the tape in relation to the plane of the tape, parallel to the faces of the tape.

Abstract: A reinforcement member including a reelable steel tape intended to be incorporated into concrete. The faces of the steel tape each include substantially rectilinear ribs arranged in at least one longitudinal row, these being substantially parallel to each other and inclined in relation to the longitudinal direction of the tape. The ribs of one of the faces of the tape are symmetrical with the ribs of the other of the faces of the tape in relation to the mid-plane of the tape, parallel to the faces of this tape.

Abstract: The method relates to the reconfiguration of meshed networks for telecommunications systems with time-division multiplexing, i.e. to a modification of the routing of the signals so that they can be sent with the utmost efficiency despite breaks in the network. In a network comprising nodes distributed in a loop and, possibly, lateral nodes, when breaks cause the loop to be split into sections, the method consists in using standby lines, if any, to connect the lines to one another and to select these standby lines to join the nodes into one network reconfigured by a path without redundancies, i.e. by a path in which the lines are crossed once and only once in each direction. Application to networks for telecommunications systems with time-division multiplexing.