Patents by Inventor Vincent Huard
Vincent Huard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11068630Abstract: Embodiments of the present technology provide a synchronous device. The synchronous device provides a first latch configured to store a data input signal during a first state of a first clock signal and a slack guard circuit. The slack guard circuit provides a delay element coupled to the first latch and configured to generate a delayed data signal, a gated-input cell coupled to the delay element and configured to propagate the delayed data signal during the first state of the first clock signal, and a comparator coupled to the first latch and the gated-input cell.Type: GrantFiled: December 20, 2019Date of Patent: July 20, 2021Assignee: Dolphin DesignInventors: Mathieu Louvat, Lionel Jure, Vincent Huard
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Publication number: 20200202062Abstract: The present disclosure relates to a synchronous device comprising: a first latch (206) having a data input receiving a data input signal (LD1) and configured to store the data input signal (LD1) during a first state of a first clock signal (CP?); and a slack guard circuit comprising: a delay element (214) having an input coupled to the data input of the first latch (206) and configured to generate, at its output, a delayed data signal (PG1); a gated-input cell (216) having an input coupled to an output of the delay element (214), the gated-input cell (216) being configured to propagate the delayed data signal (PG1) during the first state of the first clock signal (CP?); and a comparator (218) having a first input coupled to a data output of the first latch (206) and a second input coupled to an output of the gated-input cell (216).Type: ApplicationFiled: December 20, 2019Publication date: June 25, 2020Inventors: Mathieu LOUVAT, Lionel JURE, Vincent HUARD
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Patent number: 10634715Abstract: A method for determining a margin of use of an integrated circuit includes monitoring at least one sensor so as to determine at least one physical parameter representative of use of the integrated circuit, evaluating the at least one physical parameter to determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter, and calculating the margin of use for the integrated circuit from a comparison of the instantaneous state of aging with a presumed state of aging. If operation of the integrated circuit is outside the margin of use, at least one operating performance point of the integrated circuit is adjusted so as to bring operation of the integrated circuit back within the margin of use.Type: GrantFiled: May 28, 2019Date of Patent: April 28, 2020Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Vincent Huard, Chittoor Parthasarathy
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Patent number: 10585143Abstract: A flip flop includes a data input, a clock input, a test chain input, a test chain output, a monitoring circuit, and an alert transmission circuit. The monitoring circuit is adapted to generate an alert if the time between arrival of a data bit and a clock edge is less than a threshold. The alert transmission circuit is adapted to apply during a monitoring phase an alert level to the test chain output in the event of an alert generated by the monitoring circuit, and to apply the alert level to the test chain output when an alert level is received at the test chain input.Type: GrantFiled: July 10, 2018Date of Patent: March 10, 2020Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SASInventors: Pascal Urard, Florian Cacho, Vincent Huard, Alok Kumar Tripathi
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Patent number: 10514749Abstract: A system on a chip includes at least one integrated circuit that is configured to operate at least at one operating point. A monitoring circuit acquires at least the cumulative duration of activity of the at least one integrated circuit. An evaluation circuit establish at least one instantaneous state of aging of the at least one integrated circuit based on the at least one cumulative duration of activity. An adjustment circuit operates to change the at least one operating point on the basis of the at least one state of aging of the at least one integrated circuit.Type: GrantFiled: March 23, 2017Date of Patent: December 24, 2019Assignees: STMicroelectonics (Crolles 2) SAS, STMicroelectronics (Alps) SAS, STMicroelectronics SAInventors: Vincent Huard, Silvia Brini, Chittoor Parthasarathy
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Publication number: 20190285694Abstract: A method for determining a margin of use of an integrated circuit includes monitoring at least one sensor so as to determine at least one physical parameter representative of use of the integrated circuit, evaluating the at least one physical parameter to determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter, and calculating the margin of use for the integrated circuit from a comparison of the instantaneous state of aging with a presumed state of aging. If operation of the integrated circuit is outside the margin of use, at least one operating performance point of the integrated circuit is adjusted so as to bring operation of the integrated circuit back within the margin of use.Type: ApplicationFiled: May 28, 2019Publication date: September 19, 2019Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Vincent HUARD, Chittoor PARTHASARATHY
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Patent number: 10302693Abstract: A system-on-a-chip includes an integrated circuit and an estimation circuit. The estimation circuit operates to acquire at least one physical parameter representative of the use of the integrated circuit and determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter. A margin of use of the integrated circuit is then calculated by comparing the instantaneous state of aging with a presumed state of aging.Type: GrantFiled: March 24, 2017Date of Patent: May 28, 2019Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Vincent Huard, Chittoor Parthasarathy
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Publication number: 20190018062Abstract: A flip flop includes a data input, a clock input, a test chain input, a test chain output, a monitoring circuit, and an alert transmission circuit. The monitoring circuit is adapted to generate an alert if the time between arrival of a data bit and a clock edge is less than a threshold. The alert transmission circuit is adapted to apply during a monitoring phase an alert level to the test chain output in the event of an alert generated by the monitoring circuit, and to apply the alert level to the test chain output when an alert level is received at the test chain input.Type: ApplicationFiled: July 10, 2018Publication date: January 17, 2019Inventors: Pascal URARD, Florian CACHO, Vincent HUARD, Alok Kumar TRIPATHI
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Publication number: 20180323196Abstract: The disclosure concerns an integrated circuit comprising: a plurality of circuit domains, each circuit domain comprising: a plurality of transistor devices positioned over p-type and n-type wells, the transistor devices defining one or more data paths of the circuit domain; a monitoring circuit adapted to detect when the slack time of at least one of the data paths in the circuit domain falls below a threshold level and to generate an output signal on an output line based on said detection; and a biasing circuit adapted to modify a biasing voltage of the n-type and/or p-type well of the circuit domain.Type: ApplicationFiled: July 18, 2018Publication date: November 8, 2018Inventors: Florian Cacho, Vincent Huard
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Patent number: 10050037Abstract: The disclosure concerns an integrated circuit comprising: a plurality of circuit domains, each circuit domain comprising: a plurality of transistor devices positioned over p-type and n-type wells, the transistor devices defining one or more data paths of the circuit domain; a monitoring circuit adapted to detect when the slack time of at least one of the data paths in the circuit domain falls below a threshold level and to generate an output signal on an output line based on said detection; and a biasing circuit adapted to modify a biasing voltage of the n-type and/or p-type well of the circuit domain.Type: GrantFiled: May 31, 2017Date of Patent: August 14, 2018Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SASInventors: Florian Cacho, Vincent Huard
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Publication number: 20180130803Abstract: The disclosure concerns an integrated circuit comprising: a plurality of circuit domains, each circuit domain comprising: a plurality of transistor devices positioned over p-type and n-type wells, the transistor devices defining one or more data paths of the circuit domain; a monitoring circuit adapted to detect when the slack time of at least one of the data paths in the circuit domain falls below a threshold level and to generate an output signal on an output line based on said detection; and a biasing circuit adapted to modify a biasing voltage of the n-type and/or p-type well of the circuit domain.Type: ApplicationFiled: May 31, 2017Publication date: May 10, 2018Inventors: Florian Cacho, Vincent Huard
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Publication number: 20180039320Abstract: A system on a chip includes at least one integrated circuit that is configured to operate at least at one operating point. A monitoring circuit acquires at least the cumulative duration of activity of the at least one integrated circuit. An evaluation circuit establish at least one instantaneous state of aging of the at least one integrated circuit based on the at least one cumulative duration of activity. An adjustment circuit operates to change the at least one operating point on the basis of the at least one state of aging of the at least one integrated circuit.Type: ApplicationFiled: March 23, 2017Publication date: February 8, 2018Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Alps) SAS, STMicroelectronics SAInventors: Vincent Huard, Silvia Brini, Chittoor Parthasarathy
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Publication number: 20180038907Abstract: A system-on-a-chip includes an integrated circuit and an estimation circuit. The estimation circuit operates to acquire at least one physical parameter representative of the use of the integrated circuit and determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter. A margin of use of the integrated circuit is then calculated by comparing the instantaneous state of aging with a presumed state of aging.Type: ApplicationFiled: March 24, 2017Publication date: February 8, 2018Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Vincent Huard, Chittoor Parthasarathy
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Publication number: 20150142410Abstract: A method of circuit simulation includes: simulating, by a processing device, behavior of a heterojunction bipolar transistor device based on at least a first base-emitter voltage of the transistor to determine a first base or collector current density of the HBT device; and determining whether the application of the first base-emitter voltage to the HBT device will result in base current degradation by performing a first comparison of the first current density with a first current density limit.Type: ApplicationFiled: November 14, 2014Publication date: May 21, 2015Inventors: Salim Ighilahriz, Florian Cacho, Vincent Huard
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Publication number: 20120062268Abstract: Electromigration may cause a fault to appear in an integrated circuit located on a semiconductor chip. To detect such a fault, at least one resistive test structure is provided separated from the integrated circuit and located on at least one metallization level of the integrated circuit. During operation of the integrated circuit, the resistive test structure is sensed. Detection of a voltage difference between two points of the resistive test structure is indicative of a fault.Type: ApplicationFiled: September 13, 2011Publication date: March 15, 2012Applicants: STMICROELECTRONICS PVT LTD., STMICROELECTRONICS (CROLLES 2) SASInventors: Remy Chevallier, Vincent Huard, Neeraj Kapoor, Xavier Federspiel
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Patent number: 8022741Abstract: A digital electronic device is provided with a first and second sequential logic unit (SS1, SS2), each for receiving an input signal (D) and for outputting a first and second output signal (Q, QF), respectively. The electronic device furthermore comprises a comparator unit (C) for comparing the first and second output signals (Q, QF) and an adaptive clock generator unit (ACG) for generating a first and second internal clock (CK, CKF) for the first and second sequential logic unit (SS1, SS2), respectively. In a self-tuning mode, the adaptive clock generator unit (ACG) is adapted to delay the first and second internal clock signals (CK, CKF) with respect to the other internal clock signal (CKF). The delay induced by the adaptive control generator unit (ACG) is dependent on the result of the comparison unit (C). In a normal operation mode the adaptive control generator unit (ACG) is adapted to maintain the delay between the first and second internal clock signals constant.Type: GrantFiled: January 31, 2008Date of Patent: September 20, 2011Assignee: NXP B.V.Inventor: Vincent Huard
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Publication number: 20100231276Abstract: A digital electronic device is provided with a first and second sequential logic unit (SS1, SS2), each for receiving an input signal (D) and for outputting a first and second output signal (Q, QF), respectively. The electronic device furthermore comprises a comparator unit (C) for comparing the first and second output signals (Q, QF) and an adaptive clock generator unit (ACG) for generating a first and second internal clock (CK, CKF) for the first and second sequential logic unit (SS1, SS2), respectively. In a self-tuning mode, the adaptive clock generator unit (ACG) is adapted to delay the first and second internal clock signals (CK, CKF) with respect to the other internal clock signal (CKF). The delay induced by the adaptive control generator unit (ACG) is dependent on the result of the comparison unit (C). In a normal operation mode the adaptive control generator unit (ACG) is adapted to maintain the delay between the first and second internal clock signals constant.Type: ApplicationFiled: January 31, 2008Publication date: September 16, 2010Applicant: NXP, B.V.Inventor: Vincent Huard
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Patent number: 7498863Abstract: An integrated circuit comprising at least one MOS-type transistor, further comprising a system for detecting the variations of the electrical quantities of the at least one transistor, and a biasing device modifying the bias voltage of the bulk of the at least one transistor according to the variations measured by the detection system.Type: GrantFiled: August 30, 2006Date of Patent: March 3, 2009Assignee: STMicroelectronics Crolles 2 SASInventors: Mickael Denais, Vincent Huard, Chittoor Parthasarathy
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Publication number: 20070057688Abstract: An integrated circuit comprising at least one MOS-type transistor, further comprising a system for detecting the variations of the electrical quantities of the at least one transistor, and a biasing device modifying the bias voltage of the bulk of the at least one transistor according to the variations measured by the detection system.Type: ApplicationFiled: August 30, 2006Publication date: March 15, 2007Applicant: STMICROELECTRONICS CROLLES 2 SASInventors: Mickael Denais, Vincent Huard, Chittoor Parthasarathy
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Patent number: RE44922Abstract: An integrated circuit comprising at least one MOS-type transistor, further comprising a system for detecting the variations of the electrical quantities of the at least one transistor, and a biasing device modifying the bias voltage of the bulk of the at least one transistor according to the variations measured by the detection system.Type: GrantFiled: March 3, 2011Date of Patent: June 3, 2014Assignee: STMicroelectronics Crolles 2 SASInventors: Mickael Denais, Vincent Huard, Chittoor Parthasarathy