Abstract: A self-latching logic gate is disclosed which includes a first logic gate circuit for generating an output signal representative of a function of two or more input signals. The first logic gate circuit includes a first logic gate having at least two transistors, each transistor having first, second and third terminals. The first terminals of each transistor are connected to provide an output terminal for the self-latching logic gate and the first logic gate circuit. The second terminals of the transistors provide first and second data input terminals for the logic gate circuit. The third terminals of each transistor are connected to a common termination (i.e. ground). First and second complementary mode transistors are provided.

Abstract: An improved address transition detector for use in PAL circuits is disclosed. The invention provides a predetermined logical output on a transition detection signal (TDS) bus for a transition of the input address on an input pad of the PAL. The TDS bus is used to trigger a phi generator which controls sense amplifiers and latch blocks on the PAL such that the circuitry is maintained in a low power stand-by mode. The detector includes a first inverter for buffering the address input to provide a first signal, a second inverter for inverting the first signal to provide a second signal and a comparator for providing the predetermined logical level on the TDS bus for a period of time after the first signal and the second signal have changed states.

Abstract: An adaptive reference voltage generation circuit. The invention generates a reference voltage for a sense amplifier to provide bias voltages for cells in a PAL type programmable logic array. The circuit of the invention includes a reference cell having characteristics substantially similar to the cells of the array. A reference voltage supply circuit is included for providing a reference voltage in response to any changes in the characteristics of the reference cell. In accordance with the method of the invention, the reference cell is programmed and erased whenever the cells in the array are programmed and erased. Thus the characteristics of the reference cell change in accordance with changes in the characteristics of the cells of the array.

Abstract: Polarity option control logic is disclosed which provides an optimized design for a macrocell of a programmable logic array with a minimal parts count.The invention is designed for use with a register of the macrocell having first and second input paths, the first input path including an inverter, and first and second switches in each path respectively. The polarity option control logic of the present invention includes a first logic circuit for receiving a clock input and a polarity input signal and controlling the activation of the first switch in response thereto and a second logic circuit for receiving the clock input and an inverted polarity input signal and controlling the activation of the second switch in response thereto.