Patents by Inventor Vincent L. Rideout

Vincent L. Rideout has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4240845
    Abstract: A dynamic random access memory is fabricated on a monolithic chip of semiconductor material. The memory is formed of an array of memory cells controlled for reading and writing by word and bit lines which are selectively connected to the cells. Each cell is a single field effect transistor structure having improved electrical charge storage capability. The improved charge storage capability of each cell is provided by an electrical capacitance structure uniquely arranged and formed as an integral portion of the field effect transistor structure. The gate electrode of each field effect transistor structure is connected to a predetermined one of said word lines. The drain of each field effect transistor is connected to a predetermined one of said bit lines. The source of each field effect transistor structure is integrally connected to and forms a portion of the uniquely arranged electrical capacitance structure of the field effect transistor structure.
    Type: Grant
    Filed: February 4, 1980
    Date of Patent: December 23, 1980
    Assignee: International Business Machines Corporation
    Inventors: Ronald P. Esch, Robert M. Folsom, Cheng-Yih Liu, Vincent L. Rideout, Donald A. Soderman, George T. Wenning
  • Patent number: 4219834
    Abstract: A dynamic random access memory is fabricated on a monolithic chip of semiconductor material. The memory is formed of an array of memory cells controlled for reading and writing by word and bit lines which are selectively connected to the cells. Each cell is a single field effect transistor structure having improved electrical charge storage capability. The improved charge storage capability of each cell is provided by an electrical capacitance structure uniquely arranged and formed as an integral portion of the field effect transistor structure. The gate electrode of each field effect transistor structure is connected to a predetermined one of said word lines. The drain of each field effect transistor is connected to a predetermined one of said bit lines. The source of each field effect transistor structure is integrally connected to and forms a portion of the uniquely arranged electrical capacitance structure of the field effect transistor structure.
    Type: Grant
    Filed: November 11, 1977
    Date of Patent: August 26, 1980
    Assignee: International Business Machines Corporation
    Inventors: Ronald P. Esch, Robert M. Folsom, Cheng-Yih Liu, Vincent L. Rideout, Donald A. Soderman, G. Thomas Wenning
  • Patent number: 4182636
    Abstract: A fabrication method is disclosed for providing self-aligned (i.e., misregistration tolerant or "borderless") contact vias for electrical connections between metal interconnection lines and underlying doping semiconductive regions of an integrated circuit. The described method utilizes an oxidation barrier layer material which is patterned twice to provide, first, the recessed oxide isolation regions and, later, the self-aligned contact vias. An example of an n-channel FET embodiment is described wherein self-aligned contact vias are provided between aluminum interconnection lines and n-type doped source and drain regions. In the described method, at least a portion of the normally present misregistration region or border is eliminated between the boundary of a recessed isolation oxide and the boundary of the via. The latter is ultimately coincident with the boundary of an underlying doped region.
    Type: Grant
    Filed: June 30, 1978
    Date of Patent: January 8, 1980
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Dennard, Vincent L. Rideout
  • Patent number: 4183040
    Abstract: In a one transistor, one capacitor N-channel polysilicon gate MOSFET RAM, having self-aligned contacts to silicon gates, an N-implant is used to both form bottom electrodes of the capacitors and to form depletion mode FET channels in peripheral circuits. Separate polysilicon layers are used for the gates of enhancement mode FETs and for the capacitor upper electrodes and depletion FET gates.
    Type: Grant
    Filed: January 31, 1978
    Date of Patent: January 8, 1980
    Assignee: International Business Machines Corporation
    Inventor: Vincent L. Rideout
  • Patent number: 4160987
    Abstract: A field effect transistor (FET) with a unique gate structure is disclosed wherein the polycrystalline silicon (polysilicon) gate is self-aligned on its ends with respect to the conductive source and drain regions, and is self-aligned on its sides with respect to the nonconductive field isolation regions. The boundaries of these conductive and nonconductive regions determine the boundaries of the channel region of the FET. This double self-alignment feature results in a polysilicon gate, the lateral dimensions and location of which correlate directly with the lateral dimensions and location of the channel region of the FET. The unique gate fabrication technique employed according to the present invention comprises delineating lithographic patterns twice in the same polysilicon layer using the same oxidation barrier masking layer; whereby the first lithographic pattern delineates the FET device regions, and the next lithographic pattern forms the gate regions wherever the two patterns cross each other (i.e.
    Type: Grant
    Filed: June 6, 1977
    Date of Patent: July 10, 1979
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Dennard, Vincent L. Rideout
  • Patent number: 4144101
    Abstract: A process for providing ion-implanted regions in a substrate such as silicon beneath an existing layer such as silicon dioxide and being self-aligned to subsequently fabricated regions of said layer which includes providing a resist masking pattern above the existing layer wherein the resist masking pattern has vertical sidewalls (i.e., perpendicular to the upper surface of the substrate) or is undercut; ion-implanting impurities such as boron ions through the layer but not through the resist and portions of the layer beneath the resist; and depositing a layer of lift-off material such as aluminum on the existing layer and on the resist. The implantation step must be performed after providing the undercut resist masking pattern, but before depositing the layer of lift-off material in order to achieve the desired self-alignment feature. Because of the resist profile (i.e.
    Type: Grant
    Filed: June 5, 1978
    Date of Patent: March 13, 1979
    Assignee: International Business Machines Corporation
    Inventor: Vincent L. Rideout
  • Patent number: 4085498
    Abstract: Enhancement-mode field-effect transistors (FETs) and depletion-mode FETs are provided on the same semiconductive substrate using five basic, lithographic, pattern-delineating steps. The five lithographic masking steps delineate in order:(1) the field isolation regions;(2) the enhancement-mode FET gate electrodes;(3) the depletion-mode FET gate electrodes;(4) contact holes or vias to FET source and drain regions and to depletion-mode FET gates; and(5) the high electrical conductivity metallic-type interconnection pattern.The low-concentration doping required to form the depletion-mode channel regions is provided after the second but before the third pattern delineation step, while the high-concentration doping to form the source and drain regions is provided after the third pattern delineation step. In order to obtain the desired device structure, it is necessary to use two separately defined polycrystalline silicon regions for the gate electrodes of the enhancement-mode and depletion-mode FETs.
    Type: Grant
    Filed: July 2, 1976
    Date of Patent: April 25, 1978
    Assignee: International Business Machines Corporation
    Inventor: Vincent L. Rideout
  • Patent number: 4075045
    Abstract: Fabricating an integrated circuit array of FET one-device memory cells which includes providing a semiconductive substrate of a first conductive type; delineating field insulation regions; delineating polycrystalline silicon gate regions employing an oxidation barrier masking layer; introducing active impurities of a second and opposite conductive type into predetermined regions of the substrate to provide doped bit lines (FET drains), connection regions (FET sources), and lower conductive electrodes of the storage capacitors; next delineating upper polycrystalline silicon electrodes of the storage capacitors; growing silicon dioxide insulation over all portions of the structure except over the FET gate regions which are protected by the oxidation barrier masking layer; removing the oxidation barrier masking layer over the FET gates with an etchant; delineating contact holes to polycrystalline silicon capacitor electrodes and to FET sources and drains in circuits peripheral to the array of memory cells; and d
    Type: Grant
    Filed: February 9, 1976
    Date of Patent: February 21, 1978
    Assignee: International Business Machines Corporation
    Inventor: Vincent L. Rideout