Abstract: A computation graph is accessed. In the computation graph, operations to be performed are represented as interior nodes, inputs to the operations are represented as leaf nodes, and a result of the operations is represented as a root. Selected sets of the operations are combined to form respective kernels of operations. Code is generated execute the kernels of operations. The code is executed to determine the result.

Abstract: Systems and methods for obtaining a set of instructions for executing a computer program and generating executable code for the computer program based, at least in part, on scheduling operations associated with the executable code according to a polyhedral representation of a directed acyclic graph. The set of instructions may be represented as a domain-specific language. The executable code may be executable code for a specific processor architecture.

Abstract: Apparatuses, systems, and techniques to cause information to be stored in one or more memory locations based, at least in part, on one or more graphs. In at least one embodiment, a compiler analyzes one or more graphs to determine one or more sets of data items to be stored in one or more consecutive memory locations.

Abstract: Apparatuses, systems, and techniques to add operators to a compiler. In at least one embodiment, one or more operators are added to a compiler using one or more application programming interfaces (APIs).

Abstract: Apparatuses, systems, and techniques to infer information from one or more sets of data. In at least one embodiment, a processor uses one or more neural networks to infer information from one or more sets of data based, at least in part, on one or more dynamically configurable dimensions of the one or more sets of data.

Abstract: Apparatuses, systems, and techniques to determine dimensions of one or more sets of data. In at least one embodiment, a processor causes one or more dimensions of one or more sets of data to be determined using one or more dimensional constraints of the one or more sets of data.

Abstract: A computation graph is accessed. In the computation graph, operations to be performed are represented as interior nodes, inputs to the operations are represented as leaf nodes, and a result of the operations is represented as a root. Selected sets of the operations are combined to form respective kernels of operations. Code is generated execute the kernels of operations. The code is executed to determine the result.

Abstract: Apparatuses, systems, and techniques to detect loops in neural network graphs. In at least one embodiment, one or more loops are detected within one or more graphs corresponding to one or more neural networks.

Abstract: System and method of compiling a program having a mixture of host code and device code to enable Profile Guided Optimization (PGO) for device code execution. An exemplary integrated compiler can compile source code programmed to be executed by a host processor (e.g., CPU) and a co-processor (e.g., a GPU) concurrently. The compilation can generate an instrumented executable code which includes: profile instrumentation counters for the device functions; and instructions for the host processor to allocate and initialize device memory for the counters and to retrieve collected profile information from the device memory to generate instrumentation output. The output is fed back to the compiler for compiling the source code a second time to generate optimized executable code for the device functions defined in the source code.

Abstract: Apparatuses, systems, and techniques to modify performance of a neural network. In at least one embodiment, performance of one or more neural networks is modified based, at least in part, on a user-provided description of at least portions of the one or more neural networks.

Abstract: Apparatuses, systems, and techniques to combine operations. In at least one embodiment, a processor causes two or more operations in a graph to be combined based, at least in part, on another combination of two or more independent operations.

Abstract: Apparatuses, systems, and techniques to perform matrix multiplication fused with reduction using a graphics processing unit. In at least one embodiment, one or more circuits are used to multiply two or more sub-portions of one or more matrices and generate two or more vectors therefrom using two or more parallel operations.

Abstract: System and method of compiling a program having a mixture of host code and device code to enable Profile Guided Optimization (PGO) for device code execution. An exemplary integrated compiler can compile source code programmed to be executed by a host processor (e.g., CPU) and a co-processor (e.g., a GPU) concurrently. The compilation can generate an instrumented executable code which includes: profile instrumentation counters for the device functions; and instructions for the host processor to allocate and initialize device memory for the counters and to retrieve collected profile information from the device memory to generate instrumentation output. The output is fed back to the compiler for compiling the source code a second time to generate optimized executable code for the device functions defined in the source code.

Abstract: System and method of compiling a program having a mixture of host code and device code to enable Profile Guided Optimization (PGO) for device code execution. An exemplary integrated compiler can compile source code programmed to be executed by a host processor (e.g., CPU) and a co-processor (e.g., a GPU) concurrently. The compilation can generate an instrumented executable code which includes: profile instrumentation counters for the device functions; and instructions for the host processor to allocate and initialize device memory for the counters and to retrieve collected profile information from the device memory to generate instrumentation output. The output is fed back to the compiler for compiling the source code a second time to generate optimized executable code for the device functions defined in the source code.

Abstract: A computer system manages the allocation of memory to an application program using a dependency tree. The dependency tree informs a memory manager of data inputs, data outputs, and intermediate values associated with execution of the application program. The memory manager allocates a single heap structure within a physical memory. Data associated with each node of the dependency tree is allocated to the heap structure so that data input values are allocated in a contiguous block, and intermediate values are allocated separately. In various examples, as execution of the application program proceeds, the separation of intermediate values from non-intermediate values within the heap reduces memory fragmentation providing improved performance of the computer system as a whole.

Abstract: A compiler generates an accelerated version of a serial computer program that can be executed on a parallel processor. The compiler analyzes the serial computer program and generates a graph of nodes connected by edges. Each node corresponds to an operation or value set forth in the serial computer program. Each incoming edge corresponds to an operand that is specified or generated in the serial computer program. The compiler partitions the graph of nodes into two different types of partitions; a first type of partition includes one or more nodes that correspond to one or more pointwise operations, and a second type of partition includes one node that corresponds to one operation that is performed efficiently via a library. For each partition, the compiler configures a sequence of kernels that can be executed on the parallel processor to perform the operations associated with the computer program in an accelerated fashion.

Abstract: A system and method for processing source code for compilation. The method includes accessing a portion of host source code and determining whether the portion of the host source code comprises a device lambda expression. The method further includes in response to the portion of host code comprising the device lambda expression, determining a unique placeholder type instantiation based on the device lambda expression and modifying the device lambda expression based on the unique placeholder type instantiation to produce modified host source code. The method further includes sending the modified host source code to a host compiler.

Abstract: A system and method for optimizing multiple invocations of a graphics processing unit (GPU) program in Java. In one embodiment, the system includes: (1) a frontend component in a computer system and configured to compile Java bytecode associated with the a class object that implements a functional interface into Intermediate Representation (IR) code and store the IR code with the associated jogArray and (2) a collector/composer component in the computer system, associated with the frontend and configured to traverse a tree containing the multiple invocations from the result to collect the IR code and compose the IR code collected in the traversing into aggregate IR code when a result of the GPU program is explicitly requested to be transferred to a host.

Abstract: System and method of compiling a program having a mixture of host code and device code to enable Profile Guided Optimization (PGO) for device code execution. An exemplary integrated compiler can compile source code programmed to be executed by a host processor (e.g., CPU) and a co-processor (e.g., a GPU) concurrently. The compilation can generate an instrumented executable code which includes: profile instrumentation counters for the device functions; and instructions for the host processor to allocate and initialize device memory for the counters and to retrieve collected profile information from the device memory to generate instrumentation output. The output is fed back to the compiler for compiling the source code a second time to generate optimized executable code for the device functions defined in the source code.

Abstract: Compiler techniques lot inline parallelism and re-targetable parallel runtime execution of logic iterators enables selection thereof from the source code or dynamically during the object code execution.