Patents by Inventor Vinod Menezes
Vinod Menezes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11863180Abstract: In described examples, a circuit includes a switch. The switch includes first transistors and second transistors. A voltage generation circuit is coupled to the switch. A level shifter is coupled to the voltage generation circuit and is configured to receive a control signal. A logic unit is coupled to the level shifter and the voltage generation circuit. The logic unit is configured to generate a secondary signal. The first transistors are configured to receive the control signal, and the second transistors are configured to receive the secondary signal.Type: GrantFiled: April 29, 2022Date of Patent: January 2, 2024Assignee: Texas Instruments IncorporatedInventors: Divya Kaur, Muthusubramanian N. Venkateswaran, Vinod Menezes
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Publication number: 20230062353Abstract: In described examples, a circuit includes a switch. The switch includes first transistors and second transistors. A voltage generation circuit is coupled to the switch. A level shifter is coupled to the voltage generation circuit and is configured to receive a control signal. A logic unit is coupled to the level shifter and the voltage generation circuit. The logic unit is configured to generate a secondary signal. The first transistors are configured to receive the control signal, and the second transistors are configured to receive the secondary signal.Type: ApplicationFiled: April 29, 2022Publication date: March 2, 2023Inventors: Divya Kaur, Muthusubramanian N. Venkateswaran, Vinod Menezes
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Patent number: 11320478Abstract: In a method of testing a semiconductor wafer, a probe tip contacts a pad in a scribe line space between facing sides of first and second dies. The probe tip is electrically coupled to an automated test equipment (ATE). The second die is spaced apart from the first die. The scribe line space includes an interconnect extending along at least an entire length of the facing sides of the first and second dies. The pad is electrically coupled through the interconnect to at least one of the first or second dies. With the ATE, circuitry is tested in at least one of the first or second dies. The pad is electrically coupled through the interconnect to the circuitry.Type: GrantFiled: June 15, 2020Date of Patent: May 3, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rubin Ajit Parekhji, Mahesh M. Mehendale, Vinod Menezes, Vipul K. Singhal
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Patent number: 11283345Abstract: In some examples, a voltage regulator includes a first pair of switches controllable by a first clock signal having a first phase. The switches in the first pair are coupled to each other via a capacitor. The voltage regulator also includes a second pair of switches controllable by a second clock signal having a second phase. The first and second phases are non-overlapping. The switches in the second pair are coupled to each other via the capacitor.Type: GrantFiled: April 12, 2021Date of Patent: March 22, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kishalay Datta, Vinod Menezes
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Publication number: 20210234456Abstract: In some examples, a voltage regulator includes a first pair of switches controllable by a first clock signal having a first phase. The switches in the first pair are coupled to each other via a capacitor. The voltage regulator also includes a second pair of switches controllable by a second clock signal having a second phase. The first and second phases are non-overlapping. The switches in the second pair are coupled to each other via the capacitor.Type: ApplicationFiled: April 12, 2021Publication date: July 29, 2021Inventors: Kishalay Datta, Vinod Menezes
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Patent number: 10978944Abstract: In some examples, a voltage regulator includes a first pair of switches controllable by a first clock signal having a first phase. The switches in the first pair are coupled to each other via a capacitor. The voltage regulator also includes a second pair of switches controllable by a second clock signal having a second phase. The first and second phases are non-overlapping. The switches in the second pair are coupled to each other via the capacitor.Type: GrantFiled: July 19, 2018Date of Patent: April 13, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kishalay Datta, Vinod Menezes
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Publication number: 20200379031Abstract: In a method of testing a semiconductor wafer, a probe tip contacts a pad in a scribe line space between facing sides of first and second dies. The probe tip is electrically coupled to an automated test equipment (ATE). The second die is spaced apart from the first die. The scribe line space includes an interconnect extending along at least an entire length of the facing sides of the first and second dies. The pad is electrically coupled through the interconnect to at least one of the first or second dies. With the ATE, circuitry is tested in at least one of the first or second dies. The pad is electrically coupled through the interconnect to the circuitry.Type: ApplicationFiled: June 15, 2020Publication date: December 3, 2020Inventors: Rubin Ajit Parekhji, Mahesh M. Mehendale, Vinod Menezes, Vipul K. Singhal
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Publication number: 20200336141Abstract: A supply voltage supervisor circuit includes a comparator circuit. The comparator circuit includes a first input terminal, a second input terminal, a first transistor, and a second transistor. The first transistor has a first threshold voltage, and includes a first terminal coupled to the first input terminal. The second transistor has a second threshold voltage that is different from the first voltage threshold, and includes a first terminal coupled to the second input terminal, and a second terminal coupled to a second terminal of the first transistor. A trip point of the comparator circuit is based on a difference of the first threshold voltage and the second threshold voltage.Type: ApplicationFiled: April 20, 2020Publication date: October 22, 2020Inventors: Santhosh Kumar S, Divya KAUR, Rajat CHAUHAN, Jayateerth Pandurang MATHAD, Tallam VISHWANATH, Vinod MENEZES
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Patent number: 10684322Abstract: In a method of testing a semiconductor wafer including a scribe line and multiple dies, the method includes implementing a first landing pad on the scribe line, and implementing a first interconnect on the scribe line and between the first landing pad and a first cluster of the dies, thereby coupling the first landing pad to the first cluster of dies. The method also includes performing the testing of the first cluster of dies using automated test equipment (ATE) coupled to a probe tip by contacting the first landing pad with the probe tip, and applying an ATE resource to the first cluster of dies.Type: GrantFiled: January 14, 2019Date of Patent: June 16, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rubin Ajit Parekhji, Mahesh M. Mehendale, Vinod Menezes, Vipul K. Singhal
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Publication number: 20190154755Abstract: In a method of testing a semiconductor wafer including a scribe line and multiple dies, the method includes implementing a first landing pad on the scribe line, and implementing a first interconnect on the scribe line and between the first landing pad and a first cluster of the dies, thereby coupling the first landing pad to the first cluster of dies. The method also includes performing the testing of the first cluster of dies using automated test equipment (ATE) coupled to a probe tip by contacting the first landing pad with the probe tip, and applying an ATE resource to the first cluster of dies.Type: ApplicationFiled: January 14, 2019Publication date: May 23, 2019Inventors: Rubin Ajit Parekhji, Mahesh M. Mehendale, Vinod Menezes, Vipul K. Singhal
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Publication number: 20190028018Abstract: In some examples, a voltage regulator includes a first pair of switches controllable by a first clock signal having a first phase. The switches in the first pair are coupled to each other via a capacitor. The voltage regulator also includes a second pair of switches controllable by a second clock signal having a second phase. The first and second phases are non-overlapping. The switches in the second pair are coupled to each other via the capacitor.Type: ApplicationFiled: July 19, 2018Publication date: January 24, 2019Inventors: Kishalay DATTA, Vinod MENEZES
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Patent number: 10180454Abstract: A method of testing a semiconductor wafer comprising a scribe line and a plurality of dies. The method includes implementing a first landing pad on the scribe line and implementing a first interconnect on the scribe line and between the first landing pad and a first cluster of the plurality of dies, thereby coupling the first landing pad to the first cluster of dies. The method also includes performing the testing of the first cluster of dies using automated test equipment (ATE) coupled to a probe tip by contacting the first landing pad with the probe tip and applying an ATE resource to the first cluster of dies.Type: GrantFiled: April 15, 2016Date of Patent: January 15, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rubin Ajit Parekhji, Mahesh M. Mehendale, Vinod Menezes, Vipul K. Singhal
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Patent number: 10090833Abstract: A low power reset circuit includes a bias generator for receiving an operating voltage generated by a power supply and generating a bias voltage in response to the received operating voltage. The operation speed of a shaper for generating a shaped signal for indicating the operating voltage and the operation speed of a comparator for comparing a threshold reference voltage with the shaped signal are both controlled in response to the generated bias voltage. The comparator also generates a comparison signal for indicating a result of the comparison. In response to the comparison signal, a reset signal generator generates a reset signal for resetting protected circuitry powered by the operating voltage generated by the power supply.Type: GrantFiled: May 30, 2017Date of Patent: October 2, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Vinod Menezes
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Patent number: 10068638Abstract: A memory array and an integrated circuit are disclosed. The memory array includes first and second banks of memory elements and five switches. Each memory element of the first bank of memory elements is coupled to an upper rail and to a first node, while each memory element of the second bank of memory elements is coupled to a second node and to a lower rail. The first switch is coupled between the first node and the second node; the second switch is coupled between the first node and the lower rail; and the third switch is coupled between the second node and the upper rail. A fourth switch is coupled between the first node and a voltage that is one diode drop above the lower rail, and a fifth switch is coupled between the second node and a voltage that is one diode drop below the upper rail.Type: GrantFiled: December 29, 2016Date of Patent: September 4, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Vinod Menezes
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Publication number: 20180190343Abstract: A memory array and an integrated circuit are disclosed. The memory array includes first and second banks of memory elements and five switches. Each memory element of the first bank of memory elements is coupled to an upper rail and to a first node, while each memory element of the second bank of memory elements is coupled to a second node and to a lower rail. The first switch is coupled between the first node and the second node; the second switch is coupled between the first node and the lower rail; and the third switch is coupled between the second node and the upper rail. A fourth switch is coupled between the first node and a voltage that is one diode drop above the lower rail, and a fifth switch is coupled between the second node and a voltage that is one diode drop below the upper rail.Type: ApplicationFiled: December 29, 2016Publication date: July 5, 2018Inventor: Vinod Menezes
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Patent number: 10008261Abstract: A static random access memory (SRAM) includes an array of storage cells and a first sense amplifier. The array of storage cells is arranged as rows and columns. The rows correspond to word lines and the columns correspond to bit lines. The first sense amplifier includes a first transistor and a second transistor. The first sense amplifier is configured to provide a first read of a first storage cell of the array of storage cells. Based on the first read of the first storage cell failing to correctly read data stored in the first storage cell, the first sense amplifier is configured to increment a body bias of the first transistor a first time. In response to the body bias of the first transistor being incremented, the first sense amplifier is configured to provide a second read of the first storage cell.Type: GrantFiled: September 18, 2017Date of Patent: June 26, 2018Assignee: Texas Instruments IncorporatedInventor: Vinod Menezes
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Publication number: 20180005693Abstract: A static random access memory (SRAM) includes an array of storage cells and a first sense amplifier. The array of storage cells is arranged as rows and columns. The rows correspond to word lines and the columns correspond to bit lines. The first sense amplifier includes a first transistor and a second transistor. The first sense amplifier is configured to provide a first read of a first storage cell of the array of storage cells. Based on the first read of the first storage cell failing to correctly read data stored in the first storage cell, the first sense amplifier is configured to increment a body bias of the first transistor a first time. In response to the body bias of the first transistor being incremented, the first sense amplifier is configured to provide a second read of the first storage cell.Type: ApplicationFiled: September 18, 2017Publication date: January 4, 2018Inventor: Vinod Menezes
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Patent number: 9799395Abstract: A static random access memory (SRAM) includes an array of storage cells and a first sense amplifier. The array of storage cells is arranged as rows and columns. The rows correspond to word lines and the columns correspond to bit lines. The first sense amplifier includes a first transistor and a second transistor. The first sense amplifier is configured to provide a first read of a first storage cell of the array of storage cells. Based on the first read of the first storage cell failing to correctly read data stored in the first storage cell, the first sense amplifier is configured to increment a body bias of the first transistor a first time. In response to the body bias of the first transistor being incremented, the first sense amplifier is configured to provide a second read of the first storage cell.Type: GrantFiled: November 30, 2015Date of Patent: October 24, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Vinod Menezes
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Publication number: 20170294910Abstract: A low power reset circuit includes a bias generator for receiving an operating voltage generated by a power supply and generating a bias voltage in response to the received operating voltage. The operation speed of a shaper for generating a shaped signal for indicating the operating voltage and the operation speed of a comparator for comparing a threshold reference voltage with the shaped signal are both controlled in response to the generated bias voltage. The comparator also generates a comparison signal for indicating a result of the comparison. In response to the comparison signal, a reset signal generator generates a reset signal for resetting protected circuitry powered by the operating voltage generated by the power supply.Type: ApplicationFiled: May 30, 2017Publication date: October 12, 2017Inventor: Vinod Menezes
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Patent number: 9741430Abstract: A static random access memory (SRAM) features reduced write cycle power consumption. The SRAM includes an array of static storage cells and a write controller. The array of static storage cells is accessible via a plurality of word lines and a plurality of bit lines, and is arranged to access multiple bits via each of the word lines. The write controller controls writing to the static storage cells. The write controller is configured to perform consecutive writes to a plurality of addresses associated with a same one of the word lines, and to, in conjunction with the consecutive writes, perform fewer precharges of the bit lines than consecutive writes.Type: GrantFiled: October 4, 2016Date of Patent: August 22, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Vinod Menezes