Patents by Inventor Viraj Patwardhan

Viraj Patwardhan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7253078
    Abstract: An apparatus and method for forming a layer of underfill adhesive on an integrated circuit in wafer form is described. In one embodiment, the layer of underfill adhesive is disposed and partially cured on the active surface of the wafer. Once the underfill adhesive has partially cured, the wafer is singulated. The individual integrated circuits or die are then mounted onto a substrate such as a printed circuit board. When the solder balls of the integrated circuit are reflowed to form joints with corresponding contact pads on the substrate, the underfill adhesive reflows and is completely cured. In an alternative embodiment, the underfill adhesive is fully cured after it is disposed onto the active surface of the wafer.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: August 7, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Luu T. Nguyen, Hau T. Nguyen, Viraj A. Patwardhan, Nikhil Kelkar, Shahram Mostafazadeh
  • Patent number: 7135385
    Abstract: A wafer level method of forming a protective coating on the back surface of integrated circuit devices is described. In one aspect, a tape having a backcoat layer and a mount layer is applied to the back surface of a wafer. The backcoat layer is cured or set such that the backcoat layer is affixed to the back surface of the wafer. Thereafter, the mount layer of the backcoat/mount tape is removed while leaving the backcoat layer affixed to the back surface of the integrated circuit devices. In some embodiments, the mount layer includes an ultraviolet (UV) sensitive adhesive material that releases when exposed to UV light. The described arrangements can be used to form integrated circuits having very thin protective backcoatings. By way of example, opaque protective films having thickness in the range of 5 to 50 microns are readily obtainable.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: November 14, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Viraj A. Patwardhan, Lian Hee Tan, Nikhil Vishwanath Kelkar
  • Patent number: 7095116
    Abstract: An apparatus and method for providing aluminum free under bump metallization stacks in an integrated circuit device is disclosed. Included is the use of vias having substantially non-vertical sidewalls that are formed in a resilient layer, such as benzocyclobutene. In general, semiconductor wafers having a plurality of dice are created, with each die having a plurality of contact pads that are formed on the active surface of the wafer. One or more passivation layers are formed on the active surface and etched appropriately to form vias coupled to the contact pads. At least one resilient layer is then disposed atop the top passivation layer and etched appropriately to form vias aligned with and smaller than the passivation layer vias, such that at least part of the contact pads but no part of the passivation layer is exposed. A plurality of UBM stacks are then formed atop the exposed contact pads and resilient layer, with each UBM stack having a plurality of layers, none of which are aluminum layers.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: August 22, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Nikhil V. Kelkar, Viraj A. Patwardhan, King Tong Lim, A. Tharumalingam Sri Ganesh
  • Patent number: 7015064
    Abstract: Wafer level techniques for marking the back surfaces of integrated circuit devices are described. A wafer mounting tape is provided that includes releasable pigments. The pigments can be released by exposing the mounting tape to a selected frequency of electromagnetic radiation (e.g., UV light). The released pigments mark the back surface of the wafer. The exposure and pigmentation may be controlled using a variety of techniques including servo control of a light source, the use of masks or reticles or other suitable techniques. The marking may be done on any suitable back surface material including polymeric backcoatings, metalized films or directly on semiconductor materials.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: March 21, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Viraj A. Patwardhan, Nikhil Vishwanath Kelkar
  • Patent number: 6972244
    Abstract: Wafer level techniques for marking the back surfaces of integrated circuit devices are described. The back surface of the wafer is laser marked while being supported by a mount tape. In some embodiments, the mount tape is sufficiently transparent that the laser light passes through the mount tape and marks the back surface of the wafer. In other embodiments, the laser may actually burn the mounting tape (or portions thereof) during the marking process. The marking may be done on any suitable back surface material including polymeric backcoatings, metalized films or directly on semiconductor materials.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: December 6, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Viraj A. Patwardhan, Nikhil Vishwanath Kelkar, You Chye How, Tian Oon Goh, Soi Chong Low