Patents by Inventor Viraj Yashawant Sardesai
Viraj Yashawant Sardesai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10916431Abstract: Embodiments of the invention describe a method of forming an integrated circuit. The method includes forming an active semiconductor device region over a substrate. A first contact structure is formed over the active semiconductor device region, wherein the first contact structure includes a first contact liner material and a first contact body material. A conductive gate structure is formed over the active semiconductor device region, and a first gate cap material is formed on the conductive gate structure. The first contact liner material includes a first etch selectivity responsive to a first etch composition, the first contact body material includes a second etch selectivity responsive to the first etch composition, and the first gate cap material includes a third etch selectivity responsive to the first etch composition. The first etch selectivity is greater than each of the second and third etch selectivies.Type: GrantFiled: April 16, 2019Date of Patent: February 9, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Raghuveer Reddy Patlolla, Hari Prasad Amanapu, Vimal Kamineni, Sugirtha Krishnamurthy, Viraj Yashawant Sardesai, Cornelius Brown Peethala
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Publication number: 20200335345Abstract: Embodiments of the invention describe a method of forming an integrated circuit. The method includes forming an active semiconductor device region over a substrate. A first contact structure is formed over the active semiconductor device region, wherein the first contact structure includes a first contact liner material and a first contact body material. A conductive gate structure is formed over the active semiconductor device region, and a first gate cap material is formed on the conductive gate structure. The first contact liner material includes a first etch selectivity responsive to a first etch composition, the first contact body material includes a second etch selectivity responsive to the first etch composition, and the first gate cap material includes a third etch selectivity responsive to the first etch composition. The first etch selectivity is greater than each of the second and third etch selectivies.Type: ApplicationFiled: April 16, 2019Publication date: October 22, 2020Inventors: Raghuveer Reddy Patlolla, Hari Prasad Amanapu, Vimal Kamineni, Sugirtha Krishnamurthy, Viraj Yashawant Sardesai, Cornelius Brown Peethala
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Patent number: 9530684Abstract: Embodiments of the present invention provide structures and methods for heat suppression in finFET devices. Fins are formed in a semiconductor substrate. A graphene layer is formed on a lower portion of the sidewalls of the fins. A shallow trench isolation region is disposed on the structure and covers the graphene layer, while an upper portion of the fins protrudes from the shallow trench isolation region. The graphene layer may also be deposited on a top surface of the base semiconductor substrate. The graphene serves to conduct heat away from the fins more effectively than other dielectric materials.Type: GrantFiled: June 3, 2016Date of Patent: December 27, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Emre Alptekin, Viraj Yashawant Sardesai, Cung Do Tran, Reinaldo Ariel Vega
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Publication number: 20160284586Abstract: Embodiments of the present invention provide structures and methods for heat suppression in finFET devices. Fins are formed in a semiconductor substrate. A graphene layer is formed on a lower portion of the sidewalls of the fins. A shallow trench isolation region is disposed on the structure and covers the graphene layer, while an upper portion of the fins protrudes from the shallow trench isolation region. The graphene layer may also be deposited on a top surface of the base semiconductor substrate. The graphene serves to conduct heat away from the fins more effectively than other dielectric materials.Type: ApplicationFiled: June 3, 2016Publication date: September 29, 2016Inventors: Emre ALPTEKIN, Viraj Yashawant SARDESAI, Cung Do TRAN, Reinaldo Ariel VEGA
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Patent number: 9368493Abstract: Embodiments of the present invention provide structures and methods for heat suppression in finFET devices. Fins are formed in a semiconductor substrate. A graphene layer is formed on a lower portion of the sidewalls of the fins. A shallow trench isolation region is disposed on the structure and covers the graphene layer, while an upper portion of the fins protrudes from the shallow trench isolation region. The graphene layer may also be deposited on a top surface of the base semiconductor substrate. The graphene serves to conduct heat away from the fins more effectively than other dielectric materials.Type: GrantFiled: July 8, 2014Date of Patent: June 14, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Emre Alptekin, Viraj Yashawant Sardesai, Cung Do Tran, Reinaldo Ariel Vega
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Publication number: 20160013184Abstract: Embodiments of the present invention provide structures and methods for heat suppression in finFET devices. Fins are formed in a semiconductor substrate. A graphene layer is formed on a lower portion of the sidewalls of the fins. A shallow trench isolation region is disposed on the structure and covers the graphene layer, while an upper portion of the fins protrudes from the shallow trench isolation region. The graphene layer may also be deposited on a top surface of the base semiconductor substrate. The graphene serves to conduct heat away from the fins more effectively than other dielectric materials.Type: ApplicationFiled: July 8, 2014Publication date: January 14, 2016Inventors: Emre Alptekin, Viraj Yashawant Sardesai, Cung Do Tran, Reinaldo Ariel Vega
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Patent number: 9059308Abstract: Embodiments of the present invention include a semiconductor structure including two transistor structures separated by a dummy gate of a different material and methods for forming said structure. Embodiments including forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the third sacrificial gate with an insulating material. The insulating material replacing the third sacrificial gate may serve as a dummy gate to electrically isolate nearby source/drain regions. Embodiments further include forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the two sacrificial gates with metal gates while leaving the third sacrificial gate in place to serve as a dummy gate.Type: GrantFiled: August 2, 2012Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Emre Alptekin, Gregory Allen Northrop, Viraj Yashawant Sardesai, Cung Do Tran
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Publication number: 20150129939Abstract: Embodiments of the present invention provide an improved structure and method for forming high aspect ratio contacts. A horizontally formed contact etch stop layer is deposited in a narrow area where a contact is to be formed. A gas cluster ion beam (GCIB) process is used in the deposition of the horizontally formed contact etch stop layer.Type: ApplicationFiled: November 11, 2013Publication date: May 14, 2015Applicant: International Business Machines CorporationInventors: Emre Alptekin, Viraj Yashawant Sardesai, Reinaldo Ariel Vega
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Patent number: 8946081Abstract: Embodiments of the invention include a method of cleaning a semiconductor substrate of a device structure and a method of forming a silicide layer on a semiconductor substrate of a device structure. Embodiments include steps of converting a top portion of the substrate into an oxide layer and removing the oxide layer to expose a contaminant-free surface of the substrate.Type: GrantFiled: April 17, 2012Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Emre Alptekin, Ahmet Serkan Ozcan, Viraj Yashawant Sardesai, Cung Do Tran
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Publication number: 20140035045Abstract: Embodiments of the present invention include a semiconductor structure including two transistor structures separated by a dummy gate of a different material and methods for forming said structure. Embodiments including forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the third sacrificial gate with an insulating material. The insulating material replacing the third sacrificial gate may serve as a dummy gate to electrically isolate nearby source/drain regions. Embodiments further include forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the two sacrificial gates with metal gates while leaving the third sacrificial gate in place to serve as a dummy gate.Type: ApplicationFiled: August 2, 2012Publication date: February 6, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Emre Alptekin, Gregory Allen Northrop, Viraj Yashawant Sardesai, Cung Do Tran
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Publication number: 20130273737Abstract: Embodiments of the invention include a method of cleaning a semiconductor substrate of a device structure and a method of forming a silicide layer on a semiconductor substrate of a device structure. Embodiments include steps of converting a top portion of the substrate into an oxide layer and removing the oxide layer to expose a contaminant-free surface of the substrate.Type: ApplicationFiled: April 17, 2012Publication date: October 17, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Emre Alptekin, Ahmet Serkan Ozcan, Viraj Yashawant Sardesai, Cung Do Tran
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Patent number: 8420491Abstract: A structure and method for replacement metal gate (RMG) field effect transistors is disclosed. Silicide regions are formed on a raised source-drain (RSD) structure. The silicide regions form a chemical mechanical polish (CMP) stopping layer during a CMP process used to expose the gates prior to replacement. Protective layers are then applied and etched in the formation of metal contacts.Type: GrantFiled: November 9, 2010Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Henry K. Utomo, Unoh Kwon, Dimitri Anastassios Levedakis, Ravikumar Ramachandran, Viraj Yashawant Sardesai, Rajasekhar Venigalla
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Patent number: 8420542Abstract: A method of forming a reverse image pattern on a semiconductor base layer is disclosed. The method comprises depositing a transfer layer of amorphous carbon on the semiconductor base layer, depositing a resist layer on the transfer layer, creating a first pattern in the resist layer, creating the first pattern in the transfer layer, removing the resist layer, depositing a reverse mask layer, planarizing the reverse mask layer, and removing the transfer layer, thus forming a second pattern that is a reverse image of the first pattern.Type: GrantFiled: May 27, 2011Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Viraj Yashawant Sardesai, Michael P. Belyansky, Rajasekhar Venigalla
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Patent number: 8415250Abstract: A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.Type: GrantFiled: April 29, 2011Date of Patent: April 9, 2013Assignee: International Business Machines CorporationInventors: Emre Alptekin, Dong-Ick Lee, Viraj Yashawant Sardesai, Cung Do Tran, Jian Yu, Reinaldo Ariel Vega, Rajasekhar Venigalla
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Publication number: 20120302069Abstract: A method of forming a reverse image pattern on a semiconductor base layer is disclosed. The method comprises depositing a transfer layer of amorphous carbon on the semiconductor base layer, depositing a resist layer on the transfer layer, creating a first pattern in the resist layer, creating the first pattern in the transfer layer, removing the resist layer, depositing a reverse mask layer, planarizing the reverse mask layer, and removing the transfer layer, thus forming a second pattern that is a reverse image of the first pattern.Type: ApplicationFiled: May 27, 2011Publication date: November 29, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Viraj Yashawant Sardesai, Michael P. Belyansky, Rajasekhar Venigalla
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Publication number: 20120273798Abstract: A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.Type: ApplicationFiled: April 29, 2011Publication date: November 1, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Emre Alptekin, Dong-Ick Lee, Viraj Yashawant Sardesai, Cung Do Tran, Jian Yu, Reinaldo Ariel Vega, Rajasekhar Venigalla
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Publication number: 20120112290Abstract: A structure and method for replacement metal gate (RMG) field effect transistors is disclosed. Silicide regions are formed on a raised source-drain (RSD) structure. The silicide regions form a chemical mechanical polish (CMP) stopping layer during a CMP process used to expose the gates prior to replacement. Protective layers are then applied and etched in the formation of metal contacts.Type: ApplicationFiled: November 9, 2010Publication date: May 10, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Henry K. Utomo, Unoh Kwon, Dimitri Anastassios Levedakis, Ravikumar Ramachandran, Viraj Yashawant Sardesai, Rajasekhar Venigalla