Patents by Inventor Visvesvaraya Pentakota
Visvesvaraya Pentakota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10484001Abstract: A system for digitizing a sampled input value includes a digital-to-analog converter for generating an output signal as a function of (1) the sampled input value, (2) a reference value, and (3) digital codes, and a multi-bit analog-to-digital converter for determining the digital codes in first, intermediate, and subsequent cycles. Dither is dynamically added to the digital-to-analog converter in the intermediate cycle. The dither is corrected for in the subsequent cycle.Type: GrantFiled: December 15, 2018Date of Patent: November 19, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rishi Soundararajan, Visvesvaraya Pentakota, Anand Jerry George
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Patent number: 10483945Abstract: The disclosure provides an RF receiver. The RF receiver includes an input driver. The input driver receives a coarse signal, and generates an input signal. A digital step attenuator (DSA) is coupled to the input driver and receives the input signal. An analog to digital converter (ADC) is coupled to the DSA. The DSA includes a serial capacitor coupled to the input driver. The DSA also includes a sampling capacitor coupled to the ADC.Type: GrantFiled: December 22, 2017Date of Patent: November 19, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rajendrakumar Joish, Visvesvaraya Pentakota
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Patent number: 10476542Abstract: A digital step attenuator (DSA) includes a switch control circuit which receives the attenuated signal output by the DSA from a buffer and generates a tracked control signal for switches within the DSA. Some switch control circuits include a capacitor coupled to receive the buffered signal, a supply voltage, and a switch control logic sub-circuit for each switch. Each switch control logic sub-circuit receives a control signal, for either the gate or the bulk terminal of the switch, and generates the tracked control signal. In other embodiments, switch control circuits include a complementary MOSFET switching device coupled to receive a control signal, and a capacitor coupled to receive the buffered signal, both of which are connected to an output terminal for the tracked control signal. In those embodiments, the DSA includes a switch control circuit for each switch connected to the DSA output.Type: GrantFiled: February 13, 2019Date of Patent: November 12, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Neeraj Shrivastava, Rajendrakumar Joish, Shagun Dusad, Visvesvaraya Pentakota
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Publication number: 20190273601Abstract: A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.Type: ApplicationFiled: May 21, 2019Publication date: September 5, 2019Inventors: Jaiganesh BALAKRISHNAN, Shagun DUSAD, Visvesvaraya PENTAKOTA, Srinivas Kumar Reddy NARU, Sarma Sundareswara GUNTURI, Nagalinga Swamy Basayya AREMALLAPUR
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Patent number: 10367511Abstract: A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.Type: GrantFiled: July 16, 2018Date of Patent: July 30, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shagun Dusad, Visvesvaraya Pentakota, Mark Baxter Weaver, William Bright, Jiankun Hu
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Publication number: 20190222207Abstract: A comparator includes a pair of back-to-back negative-AND (NAND) gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.Type: ApplicationFiled: March 26, 2019Publication date: July 18, 2019Inventors: Rishi SOUNDARARAJAN, Visvesvaraya PENTAKOTA
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Patent number: 10341082Abstract: A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.Type: GrantFiled: February 27, 2018Date of Patent: July 2, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jaiganesh Balakrishnan, Shagun Dusad, Visvesvaraya Pentakota, Srinivas Kumar Reddy Naru, Sarma Sundareswara Gunturi, Nagalinga Swamy Basayya Aremallapur
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Patent number: 10320405Abstract: In described examples, an analog to digital converter (ADC) includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.Type: GrantFiled: March 1, 2018Date of Patent: June 11, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Srinivas Kumar Reddy Naru, Visvesvaraya Pentakota Appala, Shagun Dusad, Neeraj Shrivastava, Viswanathan Nagarajan, Ani Xavier, Rishi Soundararajan, Sai Aditya Nurani, Roswald Francis
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Patent number: 10284188Abstract: A comparator includes a pair of back-to-back negative-AND (NAND) gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.Type: GrantFiled: April 4, 2018Date of Patent: May 7, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rishi Soundararajan, Visvesvaraya Pentakota
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Patent number: 10185339Abstract: A voltage regulator that provides feedforward cancellation of power supply noise is disclosed. The voltage regulator includes a process tracking circuit that receives a supply voltage and generates a proportional voltage. A tracking capacitor is coupled to the process tracking circuit and generates an injection voltage based on the proportional voltage. An Ahuja compensated regulator generates a regulated voltage. The injection voltage is provided on a feedback path of the Ahuja compensated regulator.Type: GrantFiled: July 30, 2014Date of Patent: January 22, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shuaeb Fazeel, Eeshan Miglani, Visvesvaraya Pentakota, Shagun Dusad
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Publication number: 20180323790Abstract: A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.Type: ApplicationFiled: July 16, 2018Publication date: November 8, 2018Inventors: Shagun DUSAD, Visvesvaraya PENTAKOTA, Mark Baxter WEAVER, William BRIGHT, Jiankun HU
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Patent number: 10050632Abstract: A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.Type: GrantFiled: December 30, 2016Date of Patent: August 14, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shagun Dusad, Visvesvaraya Pentakota, Mark Baxter Weaver, William Bright, Jiankun Hu
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Patent number: 10038453Abstract: An analog-to-digital converter includes a comparator, a capacitive digital-to-analog converter (DAC), and calibration circuitry. The capacitive DAC is coupled to the comparator, and includes a plurality of capacitors. The calibration circuitry is configured to adjust a value of each of the capacitors, and includes binary search circuitry and error correction circuitry. The binary search circuitry applies a binary search over a first number of bits of a multi-bit adjustment value used to adjust the value of one of the capacitors, and averages a first number of comparator output samples to determine each of the first number of bits. The error correction circuitry applies an error correction to the multi-bit adjustment value generated by the binary search, and averages a second number of comparator output samples for the error correction. The second number of comparator output samples is greater than the first number of comparator output samples.Type: GrantFiled: October 25, 2017Date of Patent: July 31, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Anand Jerry George, Rishi Soundararajan, Visvesvaraya Pentakota
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Publication number: 20180191362Abstract: The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.Type: ApplicationFiled: March 1, 2018Publication date: July 5, 2018Inventors: Srinivas Kumar Reddy Naru, Visvesvaraya Pentakota Appala, Shagun Dusad, Neeraj Shrivastava, Viswanathan Nagarajan, Ani Xavier, Rishi Soundararajan, Sai Aditya Nurani, Roswald Francis
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Publication number: 20180191355Abstract: A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.Type: ApplicationFiled: December 30, 2016Publication date: July 5, 2018Inventors: Shagun DUSAD, Visvesvaraya PENTAKOTA, Mark Baxter WEAVER, William BRIGHT, Jiankun HU
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Publication number: 20180183409Abstract: The disclosure provides an RF receiver. The RF receiver includes an input driver. The input driver receives a coarse signal, and generates an input signal. A digital step attenuator (DSA) is coupled to the input driver and receives the input signal. An analog to digital converter (ADC) is coupled to the DSA. The DSA includes a serial capacitor coupled to the input driver. The DSA also includes a sampling capacitor coupled to the ADC.Type: ApplicationFiled: December 22, 2017Publication date: June 28, 2018Inventors: Rajendrakumar Joish, Visvesvaraya Pentakota
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Patent number: 9941893Abstract: An ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.Type: GrantFiled: April 12, 2017Date of Patent: April 10, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Srinivas Kumar Reddy Naru, Visvesvaraya Pentakota Appala, Shagun Dusad, Neeraj Shrivastava, Viswanathan Nagarajan, Ani Xavier, Rishi Soundararajan, Sai Aditya Nurani, Roswald Francis
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Publication number: 20170302287Abstract: The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.Type: ApplicationFiled: April 12, 2017Publication date: October 19, 2017Inventors: Srinivas Kumar Reddy Naru, Visvesvaraya Pentakota Appala, Shagun Dusad, Neeraj Shrivastava, Viswanathan Nagarajan, Ani Xavier, Rishi Soundararajan, Sai Aditya Nurani, Roswald Francis
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Patent number: 9748965Abstract: Disclosed examples include pipeline ADC, balancing circuits and methods to balance a load of a reference circuit to reduce non-linearity and settling effects for a reference voltage signal, in which balancing capacitors are connected to a voltage source in a pipeline stage ADC sample time period to precharge the balancing capacitors using a voltage above the reference voltage, and a selected set of the precharged balancing capacitors is connected to provide charge to the output of the reference circuit during the second time period.Type: GrantFiled: September 9, 2015Date of Patent: August 29, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Roswald Francis, Visvesvaraya A. Pentakota
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Publication number: 20170041014Abstract: The disclosure provides a current steering digital to analog converter (DAC) that includes a plurality of DAC elements. At least one DAC element of the plurality of DAC elements is coupled to a calibration circuit. The calibration circuit includes a fixed current source coupled to a primary node of the DAC element through a first estimation switch. A digital code generator is coupled to the primary node, and generates a first digital code corresponding to a primary voltage generated at the primary node. The digital code generator generates a second digital code. A correction DAC is coupled to the digital code generator and generates a bias voltage based on the second digital code. The bias voltage is provided to the DAC element such that a current flowing through each DAC element of the plurality of DAC elements is equal.Type: ApplicationFiled: February 19, 2016Publication date: February 9, 2017Inventors: Neeraj SHRIVASTAVA, Supreet JOSHI, Himanshu VARSHNEY, Jafar Sadique KAVILADATH, Visvesvaraya PENTAKOTA, Shagun DUSAD